Search

Renee R. Berry

Examiner (ID: 8148)

Most Active Art Unit
2818
Art Unit(s)
2829, 1109, 1762, 1104, 2813, 2891, 1792, 2818
Total Applications
592
Issued Applications
546
Pending Applications
22
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4205302 [patent_doc_number] => 06077781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Single step process for blanket-selective CVD aluminum deposition' [patent_app_type] => 1 [patent_app_number] => 8/620405 [patent_app_country] => US [patent_app_date] => 1996-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4179 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/077/06077781.pdf [firstpage_image] =>[orig_patent_app_number] => 620405 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/620405
Single step process for blanket-selective CVD aluminum deposition Mar 21, 1996 Issued
Array ( [id] => 3877019 [patent_doc_number] => 05728619 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-17 [patent_title] => 'Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer' [patent_app_type] => 1 [patent_app_number] => 8/618890 [patent_app_country] => US [patent_app_date] => 1996-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 8490 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/728/05728619.pdf [firstpage_image] =>[orig_patent_app_number] => 618890 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/618890
Selective reactive Ion etch (RIE) method for forming a narrow line-width high aspect ratio via through an integrated circuit layer Mar 19, 1996 Issued
Array ( [id] => 4057541 [patent_doc_number] => 05895268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'High pressure nitridation of tungsten' [patent_app_type] => 1 [patent_app_number] => 8/617208 [patent_app_country] => US [patent_app_date] => 1996-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2555 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895268.pdf [firstpage_image] =>[orig_patent_app_number] => 617208 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/617208
High pressure nitridation of tungsten Mar 17, 1996 Issued
Array ( [id] => 4004729 [patent_doc_number] => 05960320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Metal wiring layer forming method for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/610442 [patent_app_country] => US [patent_app_date] => 1996-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3636 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960320.pdf [firstpage_image] =>[orig_patent_app_number] => 610442 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/610442
Metal wiring layer forming method for semiconductor device Mar 3, 1996 Issued
Array ( [id] => 3994453 [patent_doc_number] => 05985769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Method of forming an interlayer insulating film' [patent_app_type] => 1 [patent_app_number] => 8/601658 [patent_app_country] => US [patent_app_date] => 1996-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2174 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985769.pdf [firstpage_image] =>[orig_patent_app_number] => 601658 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/601658
Method of forming an interlayer insulating film Feb 13, 1996 Issued
Array ( [id] => 3945715 [patent_doc_number] => 05953634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/600026 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 31163 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953634.pdf [firstpage_image] =>[orig_patent_app_number] => 600026 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/600026
Method of manufacturing semiconductor device Feb 11, 1996 Issued
Array ( [id] => 4191690 [patent_doc_number] => 06130158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Filling connection hole with wiring material by using centrifugal force' [patent_app_type] => 1 [patent_app_number] => 8/599646 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3883 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/130/06130158.pdf [firstpage_image] =>[orig_patent_app_number] => 599646 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/599646
Filling connection hole with wiring material by using centrifugal force Feb 11, 1996 Issued
Array ( [id] => 4151616 [patent_doc_number] => 06124142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method for analyzing minute foreign substance elements' [patent_app_type] => 1 [patent_app_number] => 8/600142 [patent_app_country] => US [patent_app_date] => 1996-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 11772 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124142.pdf [firstpage_image] =>[orig_patent_app_number] => 600142 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/600142
Method for analyzing minute foreign substance elements Feb 11, 1996 Issued
Array ( [id] => 3774256 [patent_doc_number] => 05817575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-06 [patent_title] => 'Prevention of clogging in CVD apparatus' [patent_app_type] => 1 [patent_app_number] => 8/594058 [patent_app_country] => US [patent_app_date] => 1996-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3737 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/817/05817575.pdf [firstpage_image] =>[orig_patent_app_number] => 594058 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/594058
Prevention of clogging in CVD apparatus Jan 29, 1996 Issued
Array ( [id] => 3968772 [patent_doc_number] => 05904514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Method for producing electrodes of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/591265 [patent_app_country] => US [patent_app_date] => 1996-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 8116 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/904/05904514.pdf [firstpage_image] =>[orig_patent_app_number] => 591265 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/591265
Method for producing electrodes of semiconductor device Jan 24, 1996 Issued
Array ( [id] => 3945665 [patent_doc_number] => 05953631 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Low stress, highly conformal CVD metal thin film' [patent_app_type] => 1 [patent_app_number] => 8/592870 [patent_app_country] => US [patent_app_date] => 1996-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2419 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/953/05953631.pdf [firstpage_image] =>[orig_patent_app_number] => 592870 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/592870
Low stress, highly conformal CVD metal thin film Jan 23, 1996 Issued
Array ( [id] => 3873315 [patent_doc_number] => 05824599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Protected encapsulation of catalytic layer for electroless copper interconnect' [patent_app_type] => 1 [patent_app_number] => 8/587264 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 6088 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/824/05824599.pdf [firstpage_image] =>[orig_patent_app_number] => 587264 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/587264
Protected encapsulation of catalytic layer for electroless copper interconnect Jan 15, 1996 Issued
08/587147 INTEGRATED TUNGSTEN-SILICIDE PROCESSES Jan 15, 1996 Abandoned
Array ( [id] => 3942533 [patent_doc_number] => 05946594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants' [patent_app_type] => 1 [patent_app_number] => 8/581765 [patent_app_country] => US [patent_app_date] => 1996-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2170 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946594.pdf [firstpage_image] =>[orig_patent_app_number] => 581765 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/581765
Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants Jan 1, 1996 Issued
Array ( [id] => 3967364 [patent_doc_number] => 05956613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Method for improvement of TiN CVD film quality' [patent_app_type] => 1 [patent_app_number] => 8/579383 [patent_app_country] => US [patent_app_date] => 1995-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2568 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956613.pdf [firstpage_image] =>[orig_patent_app_number] => 579383 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/579383
Method for improvement of TiN CVD film quality Dec 26, 1995 Issued
Array ( [id] => 4024510 [patent_doc_number] => 05883013 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Method of producing semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/578127 [patent_app_country] => US [patent_app_date] => 1995-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3366 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883013.pdf [firstpage_image] =>[orig_patent_app_number] => 578127 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/578127
Method of producing semiconductor device Dec 25, 1995 Issued
Array ( [id] => 3889453 [patent_doc_number] => 05834372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Pretreatment of semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 8/571052 [patent_app_country] => US [patent_app_date] => 1995-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3265 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834372.pdf [firstpage_image] =>[orig_patent_app_number] => 571052 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/571052
Pretreatment of semiconductor substrate Dec 11, 1995 Issued
Array ( [id] => 3994190 [patent_doc_number] => 05985751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Process for fabricating interconnection of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/568667 [patent_app_country] => US [patent_app_date] => 1995-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 7659 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/985/05985751.pdf [firstpage_image] =>[orig_patent_app_number] => 568667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/568667
Process for fabricating interconnection of semiconductor device Dec 6, 1995 Issued
Array ( [id] => 3832501 [patent_doc_number] => 05814560 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Metallization sidewall passivation technology for deep sub-half micrometer IC applications' [patent_app_type] => 1 [patent_app_number] => 8/564752 [patent_app_country] => US [patent_app_date] => 1995-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3647 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/814/05814560.pdf [firstpage_image] =>[orig_patent_app_number] => 564752 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/564752
Metallization sidewall passivation technology for deep sub-half micrometer IC applications Nov 28, 1995 Issued
Array ( [id] => 4139626 [patent_doc_number] => 06060387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions' [patent_app_type] => 1 [patent_app_number] => 8/574557 [patent_app_country] => US [patent_app_date] => 1995-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2040 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060387.pdf [firstpage_image] =>[orig_patent_app_number] => 574557 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/574557
Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions Nov 19, 1995 Issued
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