
Renee R. Berry
Examiner (ID: 18563)
| Most Active Art Unit | 2818 |
| Art Unit(s) | 2829, 1762, 2891, 1109, 1104, 2813, 1792, 2818 |
| Total Applications | 592 |
| Issued Applications | 546 |
| Pending Applications | 22 |
| Abandoned Applications | 24 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1005349
[patent_doc_number] => 06905944
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-14
[patent_title] => 'Sacrificial collar method for improved deep trench processing'
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[pdf_file] => patents/06/905/06905944.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/249798 | Sacrificial collar method for improved deep trench processing | May 7, 2003 | Issued |
Array
(
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[patent_doc_number] => 20030203560
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-30
[patent_title] => 'CMOS transistor having different PMOS and NMOS gate electrode structures and method of fabrication thereof'
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Array
(
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[patent_doc_number] => 06874898
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-05
[patent_title] => 'THIN FILM APPARATUS, A MANUFACTURING METHOD OF THE THIN FILM APPARATUS, AN ACTIVE MATRIX SUBSTRATE, A MANUFACTURING METHOD OF THE ACTIVE MATRIX SUBSTRATE, AND AN ELECTRO-OPTICAL APPARATUS HAVING THE ACTIVE MATRIX SUBSTRATE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/418109 | THIN FILM APPARATUS, A MANUFACTURING METHOD OF THE THIN FILM APPARATUS, AN ACTIVE MATRIX SUBSTRATE, A MANUFACTURING METHOD OF THE ACTIVE MATRIX SUBSTRATE, AND AN ELECTRO-OPTICAL APPARATUS HAVING THE ACTIVE MATRIX SUBSTRATE | Apr 17, 2003 | Issued |
Array
(
[id] => 1097460
[patent_doc_number] => 06822311
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[patent_kind] => B2
[patent_issue_date] => 2004-11-23
[patent_title] => 'DC or AC electric field assisted anneal'
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[patent_app_country] => US
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Array
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[patent_title] => 'Method for forming silicon epitaxial layer'
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Array
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Array
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[patent_title] => 'Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/378568 | Method of fabricating an integrated circuit with a dielectric layer exposed to a hydrogen-bearing nitrogen source | Mar 2, 2003 | Issued |
Array
(
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[patent_doc_number] => 06908802
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[patent_issue_date] => 2005-06-21
[patent_title] => 'Ferroelectric circuit element that can be fabricated at low temperatures and method for making the same'
[patent_app_type] => utility
[patent_app_number] => 10/377971
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Array
(
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Array
(
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[patent_issue_date] => 2006-01-10
[patent_title] => 'Method of connecting an additively and subtractively formed conductive trace and an insulative base to a semiconductor chip'
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Array
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Array
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Array
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Array
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Array
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