Search

Renee R. Berry

Examiner (ID: 18563)

Most Active Art Unit
2818
Art Unit(s)
2829, 1762, 2891, 1109, 1104, 2813, 1792, 2818
Total Applications
592
Issued Applications
546
Pending Applications
22
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6000061 [patent_doc_number] => 20020028572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Method of manufacturing an optical semiconductor module' [patent_app_type] => new [patent_app_number] => 09/945809 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2704 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20020028572.pdf [firstpage_image] =>[orig_patent_app_number] => 09945809 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945809
Method of manufacturing an optical semiconductor module Sep 4, 2001 Issued
Array ( [id] => 5798424 [patent_doc_number] => 20020008227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Method for fabricating ferro-electric thin films using a sol-gel technique' [patent_app_type] => new [patent_app_number] => 09/946909 [patent_app_country] => US [patent_app_date] => 2001-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8008 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20020008227.pdf [firstpage_image] =>[orig_patent_app_number] => 09946909 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946909
Method for fabricating ferro-electric thin films using a sol-gel technique Sep 3, 2001 Abandoned
Array ( [id] => 6618659 [patent_doc_number] => 20020064953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'Chemical mechanical polishing stopper film, process for producing the same, and method of chemical mechanical polishing' [patent_app_type] => new [patent_app_number] => 09/938589 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 14900 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20020064953.pdf [firstpage_image] =>[orig_patent_app_number] => 09938589 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/938589
Chemical mechanical polishing stopper film, process for producing the same, and method of chemical mechanical polishing Aug 26, 2001 Abandoned
Array ( [id] => 1354730 [patent_doc_number] => 06576539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Semiconductor chip assembly with interlocked conductive trace' [patent_app_type] => B1 [patent_app_number] => 09/939140 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 121 [patent_no_of_words] => 12305 [patent_no_of_claims] => 120 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/576/06576539.pdf [firstpage_image] =>[orig_patent_app_number] => 09939140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939140
Semiconductor chip assembly with interlocked conductive trace Aug 23, 2001 Issued
Array ( [id] => 7625115 [patent_doc_number] => 06724055 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Semiconductor structure having an interconnect and method of producing the semiconductor structure' [patent_app_type] => B2 [patent_app_number] => 09/930409 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 0 [patent_no_of_words] => 2317 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/724/06724055.pdf [firstpage_image] =>[orig_patent_app_number] => 09930409 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930409
Semiconductor structure having an interconnect and method of producing the semiconductor structure Aug 14, 2001 Issued
Array ( [id] => 1386400 [patent_doc_number] => 06548393 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Semiconductor chip assembly with hardened connection joint' [patent_app_type] => B1 [patent_app_number] => 09/927216 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 52 [patent_no_of_words] => 6291 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548393.pdf [firstpage_image] =>[orig_patent_app_number] => 09927216 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927216
Semiconductor chip assembly with hardened connection joint Aug 9, 2001 Issued
Array ( [id] => 6688581 [patent_doc_number] => 20030032306 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'METHOD FOR LOW TEMPERATURE CHEMICAL VAPOR DEPOSITION OF LOW-K FILMS USING SELECTED CYCLOSILOXANE AND OZONE GASES FOR SEMICONDUCTOR APPLICATIONS' [patent_app_type] => new [patent_app_number] => 09/928209 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3425 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20030032306.pdf [firstpage_image] =>[orig_patent_app_number] => 09928209 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/928209
Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications Aug 9, 2001 Issued
Array ( [id] => 6688514 [patent_doc_number] => 20030032239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-13 [patent_title] => 'Processes and structures for self-aligned contact non-volatile memory with peripheral transistors easily modifiable for various technologies and applications' [patent_app_type] => new [patent_app_number] => 09/927303 [patent_app_country] => US [patent_app_date] => 2001-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3935 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20030032239.pdf [firstpage_image] =>[orig_patent_app_number] => 09927303 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/927303
Processes and structures for self-aligned contact non-volatile memory with peripheral transistors easily modifiable for various technologies and applications Aug 9, 2001 Issued
Array ( [id] => 1324032 [patent_doc_number] => 06602743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Method of manufacturing a flat panel display' [patent_app_type] => B2 [patent_app_number] => 09/916828 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2184 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/602/06602743.pdf [firstpage_image] =>[orig_patent_app_number] => 09916828 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/916828
Method of manufacturing a flat panel display Jul 25, 2001 Issued
Array ( [id] => 1045381 [patent_doc_number] => 06868015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Semiconductor memory array of floating gate memory cells with control gate spacer portions' [patent_app_type] => utility [patent_app_number] => 09/916619 [patent_app_country] => US [patent_app_date] => 2001-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 61 [patent_no_of_words] => 14058 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/868/06868015.pdf [firstpage_image] =>[orig_patent_app_number] => 09916619 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/916619
Semiconductor memory array of floating gate memory cells with control gate spacer portions Jul 25, 2001 Issued
Array ( [id] => 1299629 [patent_doc_number] => 06624038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Capacitor electrode having uneven surface formed by using hemispherical grained silicon' [patent_app_type] => B2 [patent_app_number] => 09/908958 [patent_app_country] => US [patent_app_date] => 2001-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 7314 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624038.pdf [firstpage_image] =>[orig_patent_app_number] => 09908958 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/908958
Capacitor electrode having uneven surface formed by using hemispherical grained silicon Jul 18, 2001 Issued
Array ( [id] => 6735575 [patent_doc_number] => 20030013210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'FERROELECTRIC CIRCUIT ELEMENT THAT CAN BE FABRICATED AT LOW TEMPERATURES AND METHOD FOR MAKING THE SAME' [patent_app_type] => new [patent_app_number] => 09/907309 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2552 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20030013210.pdf [firstpage_image] =>[orig_patent_app_number] => 09907309 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/907309
Ferroelectric circuit element that can be fabricated at low temperatures and method for making the same Jul 15, 2001 Issued
Array ( [id] => 1037478 [patent_doc_number] => 06872627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Selective formation of metal gate for dual gate oxide application' [patent_app_type] => utility [patent_app_number] => 09/905408 [patent_app_country] => US [patent_app_date] => 2001-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 5145 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/872/06872627.pdf [firstpage_image] =>[orig_patent_app_number] => 09905408 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905408
Selective formation of metal gate for dual gate oxide application Jul 15, 2001 Issued
Array ( [id] => 6735623 [patent_doc_number] => 20030013258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'PHOTOMASK ESD PROTECTION AND AN ANTI-ESD POD WITH SUCH PROTECTION' [patent_app_type] => new [patent_app_number] => 09/904388 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4152 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20030013258.pdf [firstpage_image] =>[orig_patent_app_number] => 09904388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/904388
Photomask ESD protection and an anti-ESD pod with such protection Jul 11, 2001 Issued
Array ( [id] => 6651252 [patent_doc_number] => 20030008467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Darc layer for MIM process integration' [patent_app_type] => new [patent_app_number] => 09/900398 [patent_app_country] => US [patent_app_date] => 2001-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5122 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20030008467.pdf [firstpage_image] =>[orig_patent_app_number] => 09900398 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/900398
Darc layer for MIM process integration Jul 8, 2001 Issued
Array ( [id] => 1274171 [patent_doc_number] => 06649539 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Semiconductor contact fabrication method' [patent_app_type] => B1 [patent_app_number] => 09/445109 [patent_app_country] => US [patent_app_date] => 2001-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2718 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/649/06649539.pdf [firstpage_image] =>[orig_patent_app_number] => 09445109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/445109
Semiconductor contact fabrication method Jul 8, 2001 Issued
Array ( [id] => 1371614 [patent_doc_number] => 06562687 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'MIS transistor and method for making same on a semiconductor substrate' [patent_app_type] => B1 [patent_app_number] => 09/869368 [patent_app_country] => US [patent_app_date] => 2001-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4366 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562687.pdf [firstpage_image] =>[orig_patent_app_number] => 09869368 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/869368
MIS transistor and method for making same on a semiconductor substrate Jun 27, 2001 Issued
Array ( [id] => 7093209 [patent_doc_number] => 20010034117 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-25 [patent_title] => 'Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture' [patent_app_type] => new [patent_app_number] => 09/894528 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8970 [patent_no_of_claims] => 120 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20010034117.pdf [firstpage_image] =>[orig_patent_app_number] => 09894528 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894528
Microelectronic device package filled with liquid or pressurized gas and associated method of manufacture Jun 26, 2001 Issued
Array ( [id] => 6755924 [patent_doc_number] => 20030003701 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Growing copper vias or lines within a patterned resist using a copper seed layer' [patent_app_type] => new [patent_app_number] => 09/893198 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4122 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003701.pdf [firstpage_image] =>[orig_patent_app_number] => 09893198 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/893198
Growing copper vias or lines within a patterned resist using a copper seed layer Jun 26, 2001 Issued
Array ( [id] => 1500198 [patent_doc_number] => 06486002 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Tape design to reduce warpage' [patent_app_type] => B1 [patent_app_number] => 09/894718 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1103 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486002.pdf [firstpage_image] =>[orig_patent_app_number] => 09894718 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894718
Tape design to reduce warpage Jun 26, 2001 Issued
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