Renzo Rocchegiani

Array ( [id] => 6898626 [patent_doc_number] => 20010046791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'USE OF SILICON OXYNITRIDE ARC FOR METAL LAYERS' [patent_app_type] => new [patent_app_number] => 09/207562 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046791.pdf [firstpage_image] =>[orig_patent_app_number] => 09207562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4408336 [patent_doc_number] => 06309946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Reduced RC delay between adjacent substrate wiring lines' [patent_app_type] => 1 [patent_app_number] => 9/207890 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3234 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309946.pdf [firstpage_image] =>[orig_patent_app_number] => 207890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152776 [patent_doc_number] => 06124217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'In-situ SiON deposition/bake/TEOS deposition process for reduction of defects in interlevel dielectric for integrated circuit interconnects' [patent_app_type] => 1 [patent_app_number] => 9/200016 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5610 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124217.pdf [firstpage_image] =>[orig_patent_app_number] => 200016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4366699 [patent_doc_number] => 06274481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Process sequence to improve DRAM data retention' [patent_app_type] => 1 [patent_app_number] => 9/196911 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2338 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274481.pdf [firstpage_image] =>[orig_patent_app_number] => 196911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4405704 [patent_doc_number] => 06232208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Semiconductor device and method of manufacturing a semiconductor device having an improved gate electrode profile' [patent_app_type] => 1 [patent_app_number] => 9/187428 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4416 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232208.pdf [firstpage_image] =>[orig_patent_app_number] => 187428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4233816 [patent_doc_number] => 06074914 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Integration method for sidewall split gate flash transistor' [patent_app_type] => 1 [patent_app_number] => 9/182777 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074914.pdf [firstpage_image] =>[orig_patent_app_number] => 182777 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4153653 [patent_doc_number] => 06103539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method and system for nondestructive layer defect detection' [patent_app_type] => 1 [patent_app_number] => 9/178567 [patent_app_country] => US [patent_app_date] => 1998-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2879 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103539.pdf [firstpage_image] =>[orig_patent_app_number] => 178567 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7078615 [patent_doc_number] => 20010041461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'PROCESS FOR FORMING HIGH VOLTAGE JUNCTION TERMINATION EXTENSION OXIDE' [patent_app_type] => new [patent_app_number] => 09/167177 [patent_app_country] => US [patent_app_date] => 1998-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2553 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20010041461.pdf [firstpage_image] =>[orig_patent_app_number] => 09167177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4408759 [patent_doc_number] => 06265316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Etching method' [patent_app_type] => 1 [patent_app_number] => 9/166426 [patent_app_country] => US [patent_app_date] => 1998-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 3828 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265316.pdf [firstpage_image] =>[orig_patent_app_number] => 166426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4329094 [patent_doc_number] => 06313002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Ion-implantation method applicable to manufacture of a TFT for use in a liquid crystal display apparatus' [patent_app_type] => 1 [patent_app_number] => 9/160187 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4356 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/313/06313002.pdf [firstpage_image] =>[orig_patent_app_number] => 160187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1474572 [patent_doc_number] => 06387777 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Variable temperature LOCOS process' [patent_app_type] => B1 [patent_app_number] => 09/145107 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 3715 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/387/06387777.pdf [firstpage_image] =>[orig_patent_app_number] => 09145107 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1310906 [patent_doc_number] => 06613681 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Method of removing etch residues' [patent_app_type] => B1 [patent_app_number] => 09/141812 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2480 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613681.pdf [firstpage_image] =>[orig_patent_app_number] => 09141812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4354751 [patent_doc_number] => 06218313 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Process for producing semiconductor device, apparatus for optimizing film thickness, and process for optimizing film thickness' [patent_app_type] => 1 [patent_app_number] => 9/143534 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 38 [patent_no_of_words] => 7108 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218313.pdf [firstpage_image] =>[orig_patent_app_number] => 143534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4107092 [patent_doc_number] => 06022812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Vapor deposition routes to nanoporous silica' [patent_app_type] => 1 [patent_app_number] => 9/111083 [patent_app_country] => US [patent_app_date] => 1998-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 9081 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/022/06022812.pdf [firstpage_image] =>[orig_patent_app_number] => 111083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4354530 [patent_doc_number] => 06218299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Semiconductor device and method for producing the same' [patent_app_type] => 1 [patent_app_number] => 9/101244 [patent_app_country] => US [patent_app_date] => 1998-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 13624 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218299.pdf [firstpage_image] =>[orig_patent_app_number] => 101244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4117003 [patent_doc_number] => 06071799 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method of forming a contact of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/105274 [patent_app_country] => US [patent_app_date] => 1998-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2578 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071799.pdf [firstpage_image] =>[orig_patent_app_number] => 105274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4218801 [patent_doc_number] => 06040211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Semiconductors having defect denuded zones' [patent_app_type] => 1 [patent_app_number] => 9/093796 [patent_app_country] => US [patent_app_date] => 1998-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3937 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040211.pdf [firstpage_image] =>[orig_patent_app_number] => 093796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4081239 [patent_doc_number] => 06054384 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Use of hard masks during etching of openings in integrated circuits for high etch selectivity' [patent_app_type] => 1 [patent_app_number] => 9/081196 [patent_app_country] => US [patent_app_date] => 1998-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 3947 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 369 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/054/06054384.pdf [firstpage_image] =>[orig_patent_app_number] => 081196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139883 [patent_doc_number] => 06060405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method of deposition on wafer' [patent_app_type] => 1 [patent_app_number] => 9/074105 [patent_app_country] => US [patent_app_date] => 1998-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1561 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060405.pdf [firstpage_image] =>[orig_patent_app_number] => 074105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4324408 [patent_doc_number] => 06329224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Encapsulation of microelectronic assemblies' [patent_app_type] => 1 [patent_app_number] => 9/067698 [patent_app_country] => US [patent_app_date] => 1998-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 8697 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329224.pdf [firstpage_image] =>[orig_patent_app_number] => 067698 [rel_patent_id] =>[rel_patent_doc_number] =>)