Search

Renzo Rocchegiani

Examiner (ID: 276)

Most Active Art Unit
2825
Art Unit(s)
2813, 2825
Total Applications
253
Issued Applications
222
Pending Applications
9
Abandoned Applications
22

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6327497 [patent_doc_number] => 20020197852 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'Method of fabricating a barrier layer with high tensile strength' [patent_app_type] => new [patent_app_number] => 09/885040 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3128 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0197/20020197852.pdf [firstpage_image] =>[orig_patent_app_number] => 09885040 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/885040
Method of fabricating a barrier layer with high tensile strength Jun 20, 2001 Abandoned
Array ( [id] => 1288934 [patent_doc_number] => 06632747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-14 [patent_title] => 'Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile' [patent_app_type] => B2 [patent_app_number] => 09/885600 [patent_app_country] => US [patent_app_date] => 2001-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 3938 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/632/06632747.pdf [firstpage_image] =>[orig_patent_app_number] => 09885600 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/885600
Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile Jun 19, 2001 Issued
Array ( [id] => 1193023 [patent_doc_number] => 06730596 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method of and apparatus for forming interconnection' [patent_app_type] => B1 [patent_app_number] => 09/868140 [patent_app_country] => US [patent_app_date] => 2001-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 8356 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/730/06730596.pdf [firstpage_image] =>[orig_patent_app_number] => 09868140 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/868140
Method of and apparatus for forming interconnection Jun 14, 2001 Issued
Array ( [id] => 1490302 [patent_doc_number] => 06417095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method for fabricating a dual damascene structure' [patent_app_type] => B1 [patent_app_number] => 09/878880 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1725 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417095.pdf [firstpage_image] =>[orig_patent_app_number] => 09878880 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878880
Method for fabricating a dual damascene structure Jun 10, 2001 Issued
Array ( [id] => 1574863 [patent_doc_number] => 06468924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-22 [patent_title] => 'Methods of forming thin films by atomic layer deposition' [patent_app_type] => B2 [patent_app_number] => 09/871430 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2869 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/468/06468924.pdf [firstpage_image] =>[orig_patent_app_number] => 09871430 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871430
Methods of forming thin films by atomic layer deposition May 30, 2001 Issued
Array ( [id] => 6176806 [patent_doc_number] => 20020155700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-24 [patent_title] => 'Method of forming a damascene structure' [patent_app_type] => new [patent_app_number] => 09/871400 [patent_app_country] => US [patent_app_date] => 2001-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1927 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20020155700.pdf [firstpage_image] =>[orig_patent_app_number] => 09871400 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871400
Method of forming a damascene structure May 30, 2001 Abandoned
Array ( [id] => 6409341 [patent_doc_number] => 20020182857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Damascene process in intergrated circuit fabrication' [patent_app_type] => new [patent_app_number] => 09/870440 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2218 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20020182857.pdf [firstpage_image] =>[orig_patent_app_number] => 09870440 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870440
Damascene process in intergrated circuit fabrication May 28, 2001 Abandoned
Array ( [id] => 1371972 [patent_doc_number] => 06562709 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint' [patent_app_type] => B1 [patent_app_number] => 09/865367 [patent_app_country] => US [patent_app_date] => 2001-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 39 [patent_no_of_words] => 8361 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/562/06562709.pdf [firstpage_image] =>[orig_patent_app_number] => 09865367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865367
Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint May 23, 2001 Issued
Array ( [id] => 7064976 [patent_doc_number] => 20010044188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Method of fabricating memory cell' [patent_app_type] => new [patent_app_number] => 09/854590 [patent_app_country] => US [patent_app_date] => 2001-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3694 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 469 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20010044188.pdf [firstpage_image] =>[orig_patent_app_number] => 09854590 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/854590
Method of fabricating memory cell May 14, 2001 Issued
Array ( [id] => 6898597 [patent_doc_number] => 20010046762 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Method for manufacturing semiconductor device having trench filled with polysilicon' [patent_app_type] => new [patent_app_number] => 09/852690 [patent_app_country] => US [patent_app_date] => 2001-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7089 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20010046762.pdf [firstpage_image] =>[orig_patent_app_number] => 09852690 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/852690
Method for manufacturing semiconductor device having trench filled with polysilicon May 10, 2001 Issued
Array ( [id] => 1341468 [patent_doc_number] => 06586317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage' [patent_app_type] => B1 [patent_app_number] => 09/851280 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 4825 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586317.pdf [firstpage_image] =>[orig_patent_app_number] => 09851280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/851280
Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage May 7, 2001 Issued
Array ( [id] => 6224663 [patent_doc_number] => 20020004282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'Method of forming a trench isolation structure comprising annealing the oxidation barrier layer thereof in a furnace' [patent_app_type] => new [patent_app_number] => 09/847280 [patent_app_country] => US [patent_app_date] => 2001-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2656 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004282.pdf [firstpage_image] =>[orig_patent_app_number] => 09847280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/847280
Method of forming a trench isolation structure comprising annealing the oxidation barrier layer thereof in a furnace May 2, 2001 Issued
Array ( [id] => 5787473 [patent_doc_number] => 20020160603 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Method for forming salicide protected circuit with organic material' [patent_app_type] => new [patent_app_number] => 09/843750 [patent_app_country] => US [patent_app_date] => 2001-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2133 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20020160603.pdf [firstpage_image] =>[orig_patent_app_number] => 09843750 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/843750
Method for forming salicide protected circuit with organic material Apr 29, 2001 Abandoned
Array ( [id] => 5787434 [patent_doc_number] => 20020160582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'Room temperature wafer-to-wafer bonding by polydimethylsiloxane' [patent_app_type] => new [patent_app_number] => 09/841940 [patent_app_country] => US [patent_app_date] => 2001-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2122 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20020160582.pdf [firstpage_image] =>[orig_patent_app_number] => 09841940 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/841940
Room temperature wafer-to-wafer bonding by polydimethylsiloxane Apr 25, 2001 Issued
Array ( [id] => 6774341 [patent_doc_number] => 20030017679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Substrate bonding using a selenidation reaction' [patent_app_type] => new [patent_app_number] => 09/823550 [patent_app_country] => US [patent_app_date] => 2001-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8540 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20030017679.pdf [firstpage_image] =>[orig_patent_app_number] => 09823550 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/823550
Substrate bonding using a selenidation reaction Mar 29, 2001 Issued
Array ( [id] => 1119796 [patent_doc_number] => 06797604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Method for manufacturing device substrate with metal back-gate and structure formed thereby' [patent_app_type] => B2 [patent_app_number] => 09/817120 [patent_app_country] => US [patent_app_date] => 2001-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2245 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797604.pdf [firstpage_image] =>[orig_patent_app_number] => 09817120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/817120
Method for manufacturing device substrate with metal back-gate and structure formed thereby Mar 26, 2001 Issued
Array ( [id] => 6540461 [patent_doc_number] => 20020137360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Method for stabilizing low dielectric constant layer' [patent_app_type] => new [patent_app_number] => 09/814410 [patent_app_country] => US [patent_app_date] => 2001-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1354 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137360.pdf [firstpage_image] =>[orig_patent_app_number] => 09814410 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/814410
Method for stabilizing low dielectric constant layer Mar 21, 2001 Abandoned
Array ( [id] => 6889411 [patent_doc_number] => 20010024866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Method of manufacturing a transistor' [patent_app_type] => new [patent_app_number] => 09/814390 [patent_app_country] => US [patent_app_date] => 2001-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20010024866.pdf [firstpage_image] =>[orig_patent_app_number] => 09814390 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/814390
Method of manufacturing a transistor Mar 20, 2001 Issued
Array ( [id] => 6277151 [patent_doc_number] => 20020106865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-08 [patent_title] => 'Method of forming shallow trench isolation' [patent_app_type] => new [patent_app_number] => 09/812200 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1795 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20020106865.pdf [firstpage_image] =>[orig_patent_app_number] => 09812200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812200
Method of forming shallow trench isolation Mar 18, 2001 Abandoned
Array ( [id] => 6934502 [patent_doc_number] => 20010055846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-27 [patent_title] => 'Method for manufacturing a trench capacitor' [patent_app_type] => new [patent_app_number] => 09/811800 [patent_app_country] => US [patent_app_date] => 2001-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5830 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20010055846.pdf [firstpage_image] =>[orig_patent_app_number] => 09811800 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811800
Method for manufacturing a trench capacitor Mar 18, 2001 Issued
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