
Renzo Rocchegiani
Examiner (ID: 276)
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2813, 2825 |
| Total Applications | 253 |
| Issued Applications | 222 |
| Pending Applications | 9 |
| Abandoned Applications | 22 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6327497
[patent_doc_number] => 20020197852
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'Method of fabricating a barrier layer with high tensile strength'
[patent_app_type] => new
[patent_app_number] => 09/885040
[patent_app_country] => US
[patent_app_date] => 2001-06-21
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 8
[patent_no_of_words] => 3128
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[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20020197852.pdf
[firstpage_image] =>[orig_patent_app_number] => 09885040
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885040 | Method of fabricating a barrier layer with high tensile strength | Jun 20, 2001 | Abandoned |
Array
(
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[patent_doc_number] => 06632747
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-10-14
[patent_title] => 'Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile'
[patent_app_type] => B2
[patent_app_number] => 09/885600
[patent_app_country] => US
[patent_app_date] => 2001-06-20
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 3938
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[pdf_file] => patents/06/632/06632747.pdf
[firstpage_image] =>[orig_patent_app_number] => 09885600
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/885600 | Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile | Jun 19, 2001 | Issued |
Array
(
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[patent_doc_number] => 06730596
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-05-04
[patent_title] => 'Method of and apparatus for forming interconnection'
[patent_app_type] => B1
[patent_app_number] => 09/868140
[patent_app_country] => US
[patent_app_date] => 2001-06-15
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[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/06/730/06730596.pdf
[firstpage_image] =>[orig_patent_app_number] => 09868140
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/868140 | Method of and apparatus for forming interconnection | Jun 14, 2001 | Issued |
Array
(
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[patent_doc_number] => 06417095
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-09
[patent_title] => 'Method for fabricating a dual damascene structure'
[patent_app_type] => B1
[patent_app_number] => 09/878880
[patent_app_country] => US
[patent_app_date] => 2001-06-11
[patent_effective_date] => 0000-00-00
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Array
(
[id] => 1574863
[patent_doc_number] => 06468924
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[patent_kind] => B2
[patent_issue_date] => 2002-10-22
[patent_title] => 'Methods of forming thin films by atomic layer deposition'
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[patent_app_number] => 09/871430
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[patent_app_date] => 2001-05-31
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[pdf_file] => patents/06/468/06468924.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/871430 | Methods of forming thin films by atomic layer deposition | May 30, 2001 | Issued |
Array
(
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[patent_issue_date] => 2002-10-24
[patent_title] => 'Method of forming a damascene structure'
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[patent_app_number] => 09/871400
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/871400 | Method of forming a damascene structure | May 30, 2001 | Abandoned |
Array
(
[id] => 6409341
[patent_doc_number] => 20020182857
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[patent_issue_date] => 2002-12-05
[patent_title] => 'Damascene process in intergrated circuit fabrication'
[patent_app_type] => new
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[patent_app_country] => US
[patent_app_date] => 2001-05-29
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[pdf_file] => publications/A1/0182/20020182857.pdf
[firstpage_image] =>[orig_patent_app_number] => 09870440
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/870440 | Damascene process in intergrated circuit fabrication | May 28, 2001 | Abandoned |
Array
(
[id] => 1371972
[patent_doc_number] => 06562709
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-05-13
[patent_title] => 'Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint'
[patent_app_type] => B1
[patent_app_number] => 09/865367
[patent_app_country] => US
[patent_app_date] => 2001-05-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] => patents/06/562/06562709.pdf
[firstpage_image] =>[orig_patent_app_number] => 09865367
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/865367 | Semiconductor chip assembly with simultaneously electroplated contact terminal and connection joint | May 23, 2001 | Issued |
Array
(
[id] => 7064976
[patent_doc_number] => 20010044188
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-22
[patent_title] => 'Method of fabricating memory cell'
[patent_app_type] => new
[patent_app_number] => 09/854590
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[patent_app_date] => 2001-05-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/854590 | Method of fabricating memory cell | May 14, 2001 | Issued |
Array
(
[id] => 6898597
[patent_doc_number] => 20010046762
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2001-11-29
[patent_title] => 'Method for manufacturing semiconductor device having trench filled with polysilicon'
[patent_app_type] => new
[patent_app_number] => 09/852690
[patent_app_country] => US
[patent_app_date] => 2001-05-11
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 09852690
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/852690 | Method for manufacturing semiconductor device having trench filled with polysilicon | May 10, 2001 | Issued |
Array
(
[id] => 1341468
[patent_doc_number] => 06586317
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[patent_kind] => B1
[patent_issue_date] => 2003-07-01
[patent_title] => 'Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage'
[patent_app_type] => B1
[patent_app_number] => 09/851280
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/851280 | Method of forming a zener diode in a npn and pnp bipolar process flow that requires no additional steps to set the breakdown voltage | May 7, 2001 | Issued |
Array
(
[id] => 6224663
[patent_doc_number] => 20020004282
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[patent_issue_date] => 2002-01-10
[patent_title] => 'Method of forming a trench isolation structure comprising annealing the oxidation barrier layer thereof in a furnace'
[patent_app_type] => new
[patent_app_number] => 09/847280
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Array
(
[id] => 5787473
[patent_doc_number] => 20020160603
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[patent_issue_date] => 2002-10-31
[patent_title] => 'Method for forming salicide protected circuit with organic material'
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Array
(
[id] => 5787434
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[patent_issue_date] => 2002-10-31
[patent_title] => 'Room temperature wafer-to-wafer bonding by polydimethylsiloxane'
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[patent_app_number] => 09/841940
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Array
(
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[patent_title] => 'Substrate bonding using a selenidation reaction'
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Array
(
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[patent_issue_date] => 2004-09-28
[patent_title] => 'Method for manufacturing device substrate with metal back-gate and structure formed thereby'
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[patent_app_number] => 09/817120
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Array
(
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Array
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Array
(
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Array
(
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