Resha Desai

Array ( [id] => 15427705 [patent_doc_number] => 10546792 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Method for manufacturing a semiconductor product wafer [patent_app_type] => utility [patent_app_number] => 15/845361 [patent_app_country] => US [patent_app_date] => 2017-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 2749 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15845361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12648306 [patent_doc_number] => 20180107933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => WEB PAGE TRAINING METHOD AND DEVICE, AND SEARCH INTENTION IDENTIFYING METHOD AND DEVICE [patent_app_type] => utility [patent_app_number] => 15/843267 [patent_app_country] => US [patent_app_date] => 2017-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6778 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15843267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14443547 [patent_doc_number] => 20190179647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => AUTO THROTTLING OF INPUT DATA AND DATA EXECUTION USING MACHINE LEARNING AND ARTIFICIAL INTELLIGENCE [patent_app_type] => utility [patent_app_number] => 15/840324 [patent_app_country] => US [patent_app_date] => 2017-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15840324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18137210 [patent_doc_number] => 11562899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Method for transferring thin layers [patent_app_type] => utility [patent_app_number] => 16/467254 [patent_app_country] => US [patent_app_date] => 2017-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 4129 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16467254 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12596292 [patent_doc_number] => 20180090594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-29 [patent_title] => Method of Manufacturing a Semiconductor Device Having Electrode Trenches, Isolated Source Zones and Separation Structures [patent_app_type] => utility [patent_app_number] => 15/830789 [patent_app_country] => US [patent_app_date] => 2017-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7408 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15830789 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15217951 [patent_doc_number] => 20190371662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => Nucleation-Free Gap Fill ALD Process [patent_app_type] => utility [patent_app_number] => 16/467669 [patent_app_country] => US [patent_app_date] => 2017-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16467669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13378693 [patent_doc_number] => 20180240888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => METHOD FOR MANUFACTURING A TRANSISTOR AND METHOD FOR MANUFACTURING A RING OSCILLATOR USING THE SAME [patent_app_type] => utility [patent_app_number] => 15/824373 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14526333 [patent_doc_number] => 10340438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-02 [patent_title] => Laser annealing qubits for optimized frequency allocation [patent_app_type] => utility [patent_app_number] => 15/823728 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6834 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15823728 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14859607 [patent_doc_number] => 10418540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-17 [patent_title] => Adjustment of qubit frequency through annealing [patent_app_type] => utility [patent_app_number] => 15/824438 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 4589 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824438 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15611269 [patent_doc_number] => 10586704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Wafer processing method [patent_app_type] => utility [patent_app_number] => 15/824365 [patent_app_country] => US [patent_app_date] => 2017-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4344 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15824365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13921845 [patent_doc_number] => 10205048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-02-12 [patent_title] => Method for manufacturing a light emitting diode chip [patent_app_type] => utility [patent_app_number] => 15/822227 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 2389 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15822227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16280117 [patent_doc_number] => 10763157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Method for manufacturing SOI wafer [patent_app_type] => utility [patent_app_number] => 16/465879 [patent_app_country] => US [patent_app_date] => 2017-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4270 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16465879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12243493 [patent_doc_number] => 20180076356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-03-15 [patent_title] => 'VERTICAL TOPOLOGY LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 15/813396 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813396 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13070975 [patent_doc_number] => 10056272 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-21 [patent_title] => Gas-controlled bonding platform for edge defect reduction during wafer bonding [patent_app_type] => utility [patent_app_number] => 15/811738 [patent_app_country] => US [patent_app_date] => 2017-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4354 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15811738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13132353 [patent_doc_number] => 10084116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-09-25 [patent_title] => Light emitting device and light emitting device package [patent_app_type] => utility [patent_app_number] => 15/804021 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 9176 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13921705 [patent_doc_number] => 10204977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Making electrical components in handle wafers of integrated circuit packages [patent_app_type] => utility [patent_app_number] => 15/804847 [patent_app_country] => US [patent_app_date] => 2017-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4822 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15804847 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12778588 [patent_doc_number] => 20180151364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-31 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/789273 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2339 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13963285 [patent_doc_number] => 20190057987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-21 [patent_title] => FORMING METHOD OF VIA HOLE AND MANUFACTURING METHOD OF PIXEL STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/788813 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15788813 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14221293 [patent_doc_number] => 20190123031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => ELASTOMERIC LAYER FABRICATION FOR LIGHT EMITTING DIODES [patent_app_type] => utility [patent_app_number] => 15/789275 [patent_app_country] => US [patent_app_date] => 2017-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6517 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15789275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14163885 [patent_doc_number] => 20190109045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => METHODS OF FORMING CONDUCTIVE CONTACT STRUCTURES TO SEMICONDUCTOR DEVICES AND THE RESULTING STRUCTURES [patent_app_type] => utility [patent_app_number] => 15/728632 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15728632 [rel_patent_id] =>[rel_patent_doc_number] =>)