Richard A. Booth

Array ( [id] => 17709055 [patent_doc_number] => 20220209063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => ULTRA-THIN LED ELEMENT AND INKJET INK AND LIGHT SOURCE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/563333 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563333 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19495741 [patent_doc_number] => 12114480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Method of making of plurality of 3D vertical logic elements integrated with 3D memory [patent_app_type] => utility [patent_app_number] => 17/558490 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 16730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19766083 [patent_doc_number] => 12224387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Light emitting device [patent_app_type] => utility [patent_app_number] => 17/556530 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 12317 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18394907 [patent_doc_number] => 20230163128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/556972 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17917999 [patent_doc_number] => 20220320395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/556110 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17523210 [patent_doc_number] => 20220109059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => LOW TEMPERATURE POLYCRYSTALLINE SEMICONDUCTOR DEVICE AMD MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/553208 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5936 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18828924 [patent_doc_number] => 11844225 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-12 [patent_title] => Dual hydrogen barrier layer for memory devices integrated with low density film for logic structures and methods of fabrication [patent_app_type] => utility [patent_app_number] => 17/553472 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 90 [patent_no_of_words] => 47849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19231202 [patent_doc_number] => 12010854 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-06-11 [patent_title] => Multi-level hydrogen barrier layers for memory applications and methods of fabrication [patent_app_type] => utility [patent_app_number] => 17/553480 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 90 [patent_no_of_words] => 47839 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 394 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553480 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18828902 [patent_doc_number] => 11844203 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-12 [patent_title] => Conductive and insulative hydrogen barrier layer for memory devices [patent_app_type] => utility [patent_app_number] => 17/553469 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 90 [patent_no_of_words] => 47849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18874695 [patent_doc_number] => 11862517 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-02 [patent_title] => Integrated trench and via electrode for memory device applications [patent_app_type] => utility [patent_app_number] => 17/553486 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 90 [patent_no_of_words] => 47844 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 378 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18805890 [patent_doc_number] => 11839070 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-05 [patent_title] => High density dual encapsulation materials for capacitors and methods of fabrication [patent_app_type] => utility [patent_app_number] => 17/553511 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 90 [patent_no_of_words] => 47840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18891066 [patent_doc_number] => 11869843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-09 [patent_title] => Integrated trench and via electrode for memory device applications and methods of fabrication [patent_app_type] => utility [patent_app_number] => 17/553496 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 90 [patent_no_of_words] => 47836 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 407 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553496 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18805908 [patent_doc_number] => 11839088 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-12-05 [patent_title] => Integrated via and bridge electrodes for memory array applications and methods of fabrication [patent_app_type] => utility [patent_app_number] => 17/553508 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 90 [patent_no_of_words] => 47845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18892791 [patent_doc_number] => 11871584 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-01-09 [patent_title] => Multi-level hydrogen barrier layers for memory applications [patent_app_type] => utility [patent_app_number] => 17/553475 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 90 [patent_no_of_words] => 47826 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17676827 [patent_doc_number] => 20220189994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => RF SUBSTRATE STRUCTURE AND METHOD OF PRODUCTION [patent_app_type] => utility [patent_app_number] => 17/644483 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17644483 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18440181 [patent_doc_number] => 20230187476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => DUAL HYDROGEN BARRIER LAYER FOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/550904 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 47840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550904 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19797916 [patent_doc_number] => 12238915 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Method for manufacturing semiconductor structure and same [patent_app_type] => utility [patent_app_number] => 17/545239 [patent_app_country] => US [patent_app_date] => 2021-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5375 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17545239 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17486003 [patent_doc_number] => 20220093507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => STACKED CAPACITOR [patent_app_type] => utility [patent_app_number] => 17/540447 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540447 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19582660 [patent_doc_number] => 12148790 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Capacitor structure and manufacturing method thereof, and memory [patent_app_type] => utility [patent_app_number] => 17/456808 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 6373 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19945341 [patent_doc_number] => 12317491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-27 [patent_title] => Three-dimensional memory device and fabrication method for enhanced reliability [patent_app_type] => utility [patent_app_number] => 17/456751 [patent_app_country] => US [patent_app_date] => 2021-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 3465 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17456751 [rel_patent_id] =>[rel_patent_doc_number] =>)