
Richard A. Booth
Examiner (ID: 15550, Phone: (571)272-1668 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812, 1107 |
| Total Applications | 3318 |
| Issued Applications | 2851 |
| Pending Applications | 159 |
| Abandoned Applications | 345 |
Applications
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|---|---|---|---|
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