
Richard A. Booth
Examiner (ID: 13018, Phone: (571)272-1668 , Office: P/2812 )
| Most Active Art Unit | 2812 |
| Art Unit(s) | 2812, 1107 |
| Total Applications | 3294 |
| Issued Applications | 2831 |
| Pending Applications | 161 |
| Abandoned Applications | 343 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10758465
[patent_doc_number] => 20160104617
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-14
[patent_title] => 'EXCIMER LASER ANNEALING APPARATUS AND METHOD OF USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/406280
[patent_app_country] => US
[patent_app_date] => 2014-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3569
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14406280
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/406280 | Excimer laser annealing apparatus and method of using the same | Oct 15, 2014 | Issued |
Array
(
[id] => 10041948
[patent_doc_number] => 09082661
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-14
[patent_title] => 'Scanner overlay correction system and method'
[patent_app_type] => utility
[patent_app_number] => 14/514467
[patent_app_country] => US
[patent_app_date] => 2014-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 3799
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14514467
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/514467 | Scanner overlay correction system and method | Oct 14, 2014 | Issued |
Array
(
[id] => 11050868
[patent_doc_number] => 20160247828
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-08-25
[patent_title] => 'ARRAY SUBSTRATE MANUFACTURING METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/767132
[patent_app_country] => US
[patent_app_date] => 2014-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3046
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14767132
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/767132 | Array substrate manufacturing method | Oct 13, 2014 | Issued |
Array
(
[id] => 10426196
[patent_doc_number] => 20150311207
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-10-29
[patent_title] => 'Structure and Method for FinFET Device'
[patent_app_type] => utility
[patent_app_number] => 14/504258
[patent_app_country] => US
[patent_app_date] => 2014-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 27
[patent_no_of_words] => 8367
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14504258
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/504258 | Structure and method for FinFET device | Sep 30, 2014 | Issued |
Array
(
[id] => 9805841
[patent_doc_number] => 20150017786
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-15
[patent_title] => 'Method for Treating Group III Nitride Substrate and Method for Manufacturing Epitaxial Substrate'
[patent_app_type] => utility
[patent_app_number] => 14/499336
[patent_app_country] => US
[patent_app_date] => 2014-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 5465
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499336
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/499336 | Method for treating group III nitride substrate and method for manufacturing epitaxial substrate | Sep 28, 2014 | Issued |
Array
(
[id] => 10208926
[patent_doc_number] => 20150093916
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-02
[patent_title] => 'Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Non-Transitory Computer-Readable Recording Medium'
[patent_app_type] => utility
[patent_app_number] => 14/498023
[patent_app_country] => US
[patent_app_date] => 2014-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 12281
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498023
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/498023 | Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory computer-readable recording medium | Sep 25, 2014 | Issued |
Array
(
[id] => 10035337
[patent_doc_number] => 09076658
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-07-07
[patent_title] => 'High precision metal thin film liftoff technique'
[patent_app_type] => utility
[patent_app_number] => 14/496674
[patent_app_country] => US
[patent_app_date] => 2014-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 21
[patent_no_of_words] => 3225
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496674
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/496674 | High precision metal thin film liftoff technique | Sep 24, 2014 | Issued |
Array
(
[id] => 9796653
[patent_doc_number] => 20150008597
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-01-08
[patent_title] => 'Semiconductor Device and Method of Forming Sacrificial Protective Layer to Protect Semiconductor Die Edge During Singulation'
[patent_app_type] => utility
[patent_app_number] => 14/494508
[patent_app_country] => US
[patent_app_date] => 2014-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5484
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14494508
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/494508 | Semiconductor device and method of forming sacrificial protective layer to protect semiconductor die edge during singulation | Sep 22, 2014 | Issued |
Array
(
[id] => 9944085
[patent_doc_number] => 08993385
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-03-31
[patent_title] => 'Method to construct a 3D semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/491489
[patent_app_country] => US
[patent_app_date] => 2014-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 74
[patent_figures_cnt] => 89
[patent_no_of_words] => 26023
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14491489
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/491489 | Method to construct a 3D semiconductor device | Sep 18, 2014 | Issued |
Array
(
[id] => 10464106
[patent_doc_number] => 20150349121
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-12-03
[patent_title] => 'ASYMMETRIC STRESSOR DRAM'
[patent_app_type] => utility
[patent_app_number] => 14/476897
[patent_app_country] => US
[patent_app_date] => 2014-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 10898
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476897
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/476897 | Asymmetric stressor DRAM | Sep 3, 2014 | Issued |
Array
(
[id] => 10964010
[patent_doc_number] => 20140367041
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-18
[patent_title] => 'WAFER DICING USING FEMTOSECOND-BASED LASER AND PLASMA ETCH'
[patent_app_type] => utility
[patent_app_number] => 14/476060
[patent_app_country] => US
[patent_app_date] => 2014-09-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7965
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14476060
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/476060 | Wafer dicing using femtosecond-based laser and plasma etch | Sep 2, 2014 | Issued |
Array
(
[id] => 9898148
[patent_doc_number] => 20150053347
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-26
[patent_title] => 'CONTROLLING CD AND CD UNIFORMITY WITH TRIM TIME AND TEMPERATURE ON A WAFER BY WAFER BASIS'
[patent_app_type] => utility
[patent_app_number] => 14/470544
[patent_app_country] => US
[patent_app_date] => 2014-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6821
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14470544
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/470544 | Controlling CD and CD uniformity with trim time and temperature on a wafer by wafer basis | Aug 26, 2014 | Issued |
Array
(
[id] => 11585783
[patent_doc_number] => 09640434
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-02
[patent_title] => 'Method for processing an electroplated copper film in copper interconnect process'
[patent_app_type] => utility
[patent_app_number] => 14/759227
[patent_app_country] => US
[patent_app_date] => 2014-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3556
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14759227
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/759227 | Method for processing an electroplated copper film in copper interconnect process | Aug 24, 2014 | Issued |
Array
(
[id] => 9922745
[patent_doc_number] => 08980704
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2015-03-17
[patent_title] => 'Manufacturing method of thin film transistor and display array substrate using same'
[patent_app_type] => utility
[patent_app_number] => 14/467509
[patent_app_country] => US
[patent_app_date] => 2014-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 2990
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14467509
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/467509 | Manufacturing method of thin film transistor and display array substrate using same | Aug 24, 2014 | Issued |
Array
(
[id] => 10960935
[patent_doc_number] => 20140363965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-12-11
[patent_title] => 'DOUBLE SOLDER BUMPS ON SUBSTRATES FOR LOW TEMPERATURE FLIP CHIP BONDING'
[patent_app_type] => utility
[patent_app_number] => 14/467564
[patent_app_country] => US
[patent_app_date] => 2014-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 8381
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14467564
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/467564 | Double solder bumps on substrates for low temperature flip chip bonding | Aug 24, 2014 | Issued |
Array
(
[id] => 11328466
[patent_doc_number] => 20160359078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-12-08
[patent_title] => 'COMPOSITION FOR FORMING N-TYPE DIFFUSION LAYER, METHOD FOR FORMING N-TYPE DIFFUSION LAYER, METHOD OF PRODUCING SEMICONDUCTOR SUBSTRATE WITH N-TYPE DIFFUSION LAYER, AND METHOD FOR PRODUCING PHOTOVOLTAIC CELL ELEMENT'
[patent_app_type] => utility
[patent_app_number] => 14/913863
[patent_app_country] => US
[patent_app_date] => 2014-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 14382
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14913863
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/913863 | COMPOSITION FOR FORMING N-TYPE DIFFUSION LAYER, METHOD FOR FORMING N-TYPE DIFFUSION LAYER, METHOD OF PRODUCING SEMICONDUCTOR SUBSTRATE WITH N-TYPE DIFFUSION LAYER, AND METHOD FOR PRODUCING PHOTOVOLTAIC CELL ELEMENT | Aug 19, 2014 | Abandoned |
Array
(
[id] => 10703437
[patent_doc_number] => 20160049584
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-02-18
[patent_title] => 'OXIDE FILM SCHEME FOR RRAM STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 14/459361
[patent_app_country] => US
[patent_app_date] => 2014-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5568
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14459361
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/459361 | Oxide film scheme for RRAM structure | Aug 13, 2014 | Issued |
Array
(
[id] => 10531409
[patent_doc_number] => 09257554
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-09
[patent_title] => 'Split gate embedded memory technology and method of manufacturing thereof'
[patent_app_type] => utility
[patent_app_number] => 14/458265
[patent_app_country] => US
[patent_app_date] => 2014-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 14840
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458265
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/458265 | Split gate embedded memory technology and method of manufacturing thereof | Aug 12, 2014 | Issued |
Array
(
[id] => 10946011
[patent_doc_number] => 20140349032
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-27
[patent_title] => 'FILM DEPOSITION METHOD'
[patent_app_type] => utility
[patent_app_number] => 14/458319
[patent_app_country] => US
[patent_app_date] => 2014-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 13439
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458319
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/458319 | Film deposition method | Aug 12, 2014 | Issued |
Array
(
[id] => 11300627
[patent_doc_number] => 09508637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-11-29
[patent_title] => 'Protrusion bump pads for bond-on-trace processing'
[patent_app_type] => utility
[patent_app_number] => 14/456812
[patent_app_country] => US
[patent_app_date] => 2014-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 39
[patent_no_of_words] => 9852
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14456812
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/456812 | Protrusion bump pads for bond-on-trace processing | Aug 10, 2014 | Issued |