Richard A. Booth

Array ( [id] => 18396771 [patent_doc_number] => 20230164992 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-25 [patent_title] => METHOD FOR MAKING ACTIVE AREA AIR GAP [patent_app_type] => utility [patent_app_number] => 18/152868 [patent_app_country] => US [patent_app_date] => 2023-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3894 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152868 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19024910 [patent_doc_number] => 20240081081 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => FERROELECTRIC MEMORY DEVICE AND SEMICONDUCTOR DIE [patent_app_type] => utility [patent_app_number] => 18/152151 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8753 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19024907 [patent_doc_number] => 20240081078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => MEMORY DEVICE AND METHOD OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/152751 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19229792 [patent_doc_number] => 12009436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-11 [patent_title] => Memory cells and integrated assemblies having charge-trapping-material with trap-enhancing-additive [patent_app_type] => utility [patent_app_number] => 18/094377 [patent_app_country] => US [patent_app_date] => 2023-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5484 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19146541 [patent_doc_number] => 20240145571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-02 [patent_title] => INSERTING INHIBITION LAYER FOR INDUCING ANTIFERROELECTRICITY TO FERROELECTRIC STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/150259 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9595 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18360797 [patent_doc_number] => 20230142388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-11 [patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/150770 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150770 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20276425 [patent_doc_number] => 12446214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Semiconductor structure [patent_app_type] => utility [patent_app_number] => 18/150245 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2225 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18150245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18406233 [patent_doc_number] => 20230167584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => THERMAL CONTROL FOR FORMATION AND PROCESSING OF ALUMINUM NITRIDE [patent_app_type] => utility [patent_app_number] => 18/093428 [patent_app_country] => US [patent_app_date] => 2023-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093428 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20831168 [patent_doc_number] => 12684767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-07-14 [patent_title] => Structure with buried doped region for coupling source line contact to gate structure of memory cell [patent_app_type] => utility [patent_app_number] => 18/149733 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 0 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149733 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20553200 [patent_doc_number] => 12564014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Method and apparatus for substrate temperature control [patent_app_type] => utility [patent_app_number] => 18/093139 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18745592 [patent_doc_number] => 20230354586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-02 [patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/149750 [patent_app_country] => US [patent_app_date] => 2023-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10063 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18149750 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20597912 [patent_doc_number] => 12581649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Semiconductor device, fabrication method, and memory system [patent_app_type] => utility [patent_app_number] => 18/092109 [patent_app_country] => US [patent_app_date] => 2022-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 7956 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18092109 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19271527 [patent_doc_number] => 20240215234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => MEMORY DEVICES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/090931 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20509021 [patent_doc_number] => 12543313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-03 [patent_title] => Semiconductor structure and its fabrication method, memory and memory system [patent_app_type] => utility [patent_app_number] => 18/091146 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 0 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091146 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19271511 [patent_doc_number] => 20240215218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-27 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/088944 [patent_app_country] => US [patent_app_date] => 2022-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6650 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088944 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20217618 [patent_doc_number] => 12414287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Method of fabricating semiconductor device [patent_app_type] => utility [patent_app_number] => 18/088370 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 3057 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20552930 [patent_doc_number] => 12563738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/069398 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 5197 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18069398 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18336029 [patent_doc_number] => 20230127978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => METHOD OF FABRICATING SUPER-JUNCTION BASED VERTICAL GALLIUM NITRIDE JFET AND MOSFET POWER DEVICES [patent_app_type] => utility [patent_app_number] => 18/085985 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15075 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18322098 [patent_doc_number] => 20230120226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR DEVICE HAVING A MAIN TRANSISTOR, A SENSE TRANSISTOR, AND A BYPASS DIODE STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/085756 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6840 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18085756 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18336577 [patent_doc_number] => 20230128526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => DOPED POLAR LAYERS AND SEMICONDUCTOR DEVICE INCORPORATING SAME [patent_app_type] => utility [patent_app_number] => 18/068438 [patent_app_country] => US [patent_app_date] => 2022-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18068438 [rel_patent_id] =>[rel_patent_doc_number] =>)