Search

Richard B. Franklin

Examiner (ID: 6480, Phone: (571)272-0669 , Office: P/2181 )

Most Active Art Unit
2181
Art Unit(s)
2181
Total Applications
816
Issued Applications
655
Pending Applications
52
Abandoned Applications
132

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17372041 [patent_doc_number] => 20220027093 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => MEMORY WITH VARIABLE ACCESS GRANULARITY [patent_app_type] => utility [patent_app_number] => 17/428105 [patent_app_country] => US [patent_app_date] => 2020-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6261 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17428105 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/428105
Memory with variable access granularity Feb 4, 2020 Issued
Array ( [id] => 17121175 [patent_doc_number] => 11132310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => SSD architecture for FPGA based acceleration [patent_app_type] => utility [patent_app_number] => 16/752612 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 43698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752612
SSD architecture for FPGA based acceleration Jan 23, 2020 Issued
Array ( [id] => 17121175 [patent_doc_number] => 11132310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => SSD architecture for FPGA based acceleration [patent_app_type] => utility [patent_app_number] => 16/752612 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 43698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752612
SSD architecture for FPGA based acceleration Jan 23, 2020 Issued
Array ( [id] => 17121175 [patent_doc_number] => 11132310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => SSD architecture for FPGA based acceleration [patent_app_type] => utility [patent_app_number] => 16/752612 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 43698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752612
SSD architecture for FPGA based acceleration Jan 23, 2020 Issued
Array ( [id] => 17121175 [patent_doc_number] => 11132310 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-28 [patent_title] => SSD architecture for FPGA based acceleration [patent_app_type] => utility [patent_app_number] => 16/752612 [patent_app_country] => US [patent_app_date] => 2020-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 43698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16752612 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/752612
SSD architecture for FPGA based acceleration Jan 23, 2020 Issued
Array ( [id] => 17151262 [patent_doc_number] => 11144339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-12 [patent_title] => Optimizing access to production data [patent_app_type] => utility [patent_app_number] => 16/731971 [patent_app_country] => US [patent_app_date] => 2019-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8480 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16731971 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/731971
Optimizing access to production data Dec 30, 2019 Issued
Array ( [id] => 17164723 [patent_doc_number] => 11150819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Controller for allocating memory blocks, operation method of the controller, and memory system including the controller [patent_app_type] => utility [patent_app_number] => 16/730579 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730579 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730579
Controller for allocating memory blocks, operation method of the controller, and memory system including the controller Dec 29, 2019 Issued
Array ( [id] => 15870697 [patent_doc_number] => 20200142752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => PHYSICAL PARTITIONING OF COMPUTING RESOURCES FOR SERVER VIRTUALIZATION [patent_app_type] => utility [patent_app_number] => 16/730430 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8716 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730430 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730430
PHYSICAL PARTITIONING OF COMPUTING RESOURCES FOR SERVER VIRTUALIZATION Dec 29, 2019 Abandoned
Array ( [id] => 17469202 [patent_doc_number] => 11275679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-15 [patent_title] => Separate cores for media management of a memory sub-system [patent_app_type] => utility [patent_app_number] => 16/730886 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8166 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16730886 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/730886
Separate cores for media management of a memory sub-system Dec 29, 2019 Issued
Array ( [id] => 16438979 [patent_doc_number] => 20200356305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => MEMORY DEVICE INCLUDING A PROCESSING CIRCUIT, MEMORY CONTROLLER CONTROLLING THE MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/711274 [patent_app_country] => US [patent_app_date] => 2019-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16711274 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/711274
Memory device including a processing circuit, memory controller controlling the memory device and memory system including the memory device Dec 10, 2019 Issued
Array ( [id] => 16178906 [patent_doc_number] => 20200225874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => SYSTEMS AND METHODS FOR MANAGING COMMUNICATION BETWEEN NVME-SSD STORAGE DEVICE(S) AND NVME-OF HOST UNIT [patent_app_type] => utility [patent_app_number] => 16/704206 [patent_app_country] => US [patent_app_date] => 2019-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9350 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16704206 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/704206
Systems and methods for managing communication between NVMe-SSD storage device(s) and NVMe-of host unit Dec 4, 2019 Issued
Array ( [id] => 17744446 [patent_doc_number] => 11392515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Cache architecture for a storage device [patent_app_type] => utility [patent_app_number] => 16/963110 [patent_app_country] => US [patent_app_date] => 2019-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 11890 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16963110 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/963110
Cache architecture for a storage device Dec 2, 2019 Issued
Array ( [id] => 17969927 [patent_doc_number] => 11487458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Risk detection of data loss for 5G enabled devices [patent_app_type] => utility [patent_app_number] => 16/695344 [patent_app_country] => US [patent_app_date] => 2019-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6172 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16695344 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/695344
Risk detection of data loss for 5G enabled devices Nov 25, 2019 Issued
Array ( [id] => 16856935 [patent_doc_number] => 20210157680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-27 [patent_title] => PROTECTING STORAGE BACKUP CONFIGURATION [patent_app_type] => utility [patent_app_number] => 16/692157 [patent_app_country] => US [patent_app_date] => 2019-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16692157 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/692157
Protecting storage backup configuration Nov 21, 2019 Issued
Array ( [id] => 18079613 [patent_doc_number] => 20220405225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => DEVICES TO SELECT STORAGE DEVICE PROTOCOLS [patent_app_type] => utility [patent_app_number] => 17/777205 [patent_app_country] => US [patent_app_date] => 2019-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4070 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17777205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/777205
DEVICES TO SELECT STORAGE DEVICE PROTOCOLS Nov 17, 2019 Abandoned
Array ( [id] => 15501223 [patent_doc_number] => 20200050800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => METHOD AND APPARATUS FOR DATA ENCRYPTION USING A STANDARDIZED DATA STORAGE AND RETRIEVAL PROTOCOL [patent_app_type] => utility [patent_app_number] => 16/659568 [patent_app_country] => US [patent_app_date] => 2019-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6206 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16659568 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/659568
METHOD AND APPARATUS FOR DATA ENCRYPTION USING A STANDARDIZED DATA STORAGE AND RETRIEVAL PROTOCOL Oct 20, 2019 Abandoned
Array ( [id] => 16729866 [patent_doc_number] => 20210097013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-01 [patent_title] => ACTIVE BRIDGE CHIPLET WITH INTEGRATED CACHE [patent_app_type] => utility [patent_app_number] => 16/585452 [patent_app_country] => US [patent_app_date] => 2019-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5504 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16585452 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/585452
Active bridge chiplet with integrated cache Sep 26, 2019 Issued
Array ( [id] => 16623588 [patent_doc_number] => 20210042241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-11 [patent_title] => USING INSERTION POINTS TO DETERMINE LOCATIONS IN A CACHE LIST AT WHICH TO INDICATE TRACKS IN A SHARED CACHE ACCESSED BY A PLURALITY OF PROCESSORS [patent_app_type] => utility [patent_app_number] => 16/534692 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534692
Using insertion points to determine locations in a cache list at which to indicate tracks in a shared cache accessed by a plurality of processors Aug 6, 2019 Issued
Array ( [id] => 17151158 [patent_doc_number] => 11144235 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-10-12 [patent_title] => System and method for evaluating memory system performance [patent_app_type] => utility [patent_app_number] => 16/534527 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5906 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534527
System and method for evaluating memory system performance Aug 6, 2019 Issued
Array ( [id] => 16285201 [patent_doc_number] => 20200278803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-03 [patent_title] => INFORMATION PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING PROGRAM [patent_app_type] => utility [patent_app_number] => 16/533799 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16533799 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/533799
Information processing apparatus and non-transitory computer readable medium storing program Aug 6, 2019 Issued
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