Search

Richard B. Franklin

Examiner (ID: 13919, Phone: (571)272-0669 , Office: P/2181 )

Most Active Art Unit
2181
Art Unit(s)
2181
Total Applications
818
Issued Applications
655
Pending Applications
54
Abandoned Applications
132

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13693311 [patent_doc_number] => 20170357610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => SPLIT NVME SSD IMPLEMENTATION USING NVME OVER FABRICS PROTOCOL [patent_app_type] => utility [patent_app_number] => 15/623194 [patent_app_country] => US [patent_app_date] => 2017-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 759 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15623194 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/623194
SPLIT NVME SSD IMPLEMENTATION USING NVME OVER FABRICS PROTOCOL Jun 13, 2017 Abandoned
Array ( [id] => 15313137 [patent_doc_number] => 10521273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Physical partitioning of computing resources for server virtualization [patent_app_type] => utility [patent_app_number] => 15/617190 [patent_app_country] => US [patent_app_date] => 2017-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8684 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15617190 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/617190
Physical partitioning of computing resources for server virtualization Jun 7, 2017 Issued
Array ( [id] => 14571081 [patent_doc_number] => 20190213147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-11 [patent_title] => STORAGE SYSTEM AND MAPPING METHOD [patent_app_type] => utility [patent_app_number] => 16/333640 [patent_app_country] => US [patent_app_date] => 2017-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16333640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/333640
STORAGE SYSTEM AND MAPPING METHOD May 21, 2017 Abandoned
Array ( [id] => 14426741 [patent_doc_number] => 10318174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Computer system for performing adaptive interrupt control and method for controlling interrupt thereof [patent_app_type] => utility [patent_app_number] => 15/598850 [patent_app_country] => US [patent_app_date] => 2017-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6560 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15598850 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/598850
Computer system for performing adaptive interrupt control and method for controlling interrupt thereof May 17, 2017 Issued
Array ( [id] => 13568795 [patent_doc_number] => 20180335945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => Prioritizing Dedicated Host Ports When N-Port ID Virtualization is enabled in a Storage Controller [patent_app_type] => utility [patent_app_number] => 15/597428 [patent_app_country] => US [patent_app_date] => 2017-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7180 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15597428 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/597428
Prioritizing dedicated host ports when N-port ID virtualization is enabled in a storage controller May 16, 2017 Issued
Array ( [id] => 13568813 [patent_doc_number] => 20180335954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-22 [patent_title] => SYSTEMS AND METHODS FOR HARDWARE-BASED RAID ACCELERATION [patent_app_type] => utility [patent_app_number] => 15/596960 [patent_app_country] => US [patent_app_date] => 2017-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5177 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15596960 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/596960
Systems and methods for hardware-based RAID acceleration May 15, 2017 Issued
Array ( [id] => 15758037 [patent_doc_number] => 10621132 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-14 [patent_title] => Auto address generation for switch network [patent_app_type] => utility [patent_app_number] => 15/588321 [patent_app_country] => US [patent_app_date] => 2017-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15588321 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/588321
Auto address generation for switch network May 4, 2017 Issued
Array ( [id] => 17325359 [patent_doc_number] => 11216371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-04 [patent_title] => Cache memory and method for controlling the same [patent_app_type] => utility [patent_app_number] => 16/480123 [patent_app_country] => US [patent_app_date] => 2017-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8196 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16480123 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/480123
Cache memory and method for controlling the same Mar 26, 2017 Issued
Array ( [id] => 11629675 [patent_doc_number] => 20170139864 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-18 [patent_title] => 'SERIAL BUS ELECTRICAL TERMINATION CONTROL' [patent_app_type] => utility [patent_app_number] => 15/419443 [patent_app_country] => US [patent_app_date] => 2017-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15419443 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/419443
Serial bus electrical termination control Jan 29, 2017 Issued
Array ( [id] => 11853668 [patent_doc_number] => 20170228160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'METHOD AND DEVICE TO DISTRIBUTE CODE AND DATA STORES BETWEEN VOLATILE MEMORY AND NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 15/408984 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6474 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15408984 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/408984
METHOD AND DEVICE TO DISTRIBUTE CODE AND DATA STORES BETWEEN VOLATILE MEMORY AND NON-VOLATILE MEMORY Jan 17, 2017 Abandoned
Array ( [id] => 15106589 [patent_doc_number] => 10474620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-12 [patent_title] => System and method for improving peripheral component interface express bus performance in an information handling system [patent_app_type] => utility [patent_app_number] => 15/397003 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397003 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/397003
System and method for improving peripheral component interface express bus performance in an information handling system Jan 2, 2017 Issued
Array ( [id] => 13891671 [patent_doc_number] => 10198383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-05 [patent_title] => Systems and methods of adjusting an interface bus speed [patent_app_type] => utility [patent_app_number] => 15/396482 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 14463 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396482 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396482
Systems and methods of adjusting an interface bus speed Dec 30, 2016 Issued
Array ( [id] => 12892144 [patent_doc_number] => 20180189223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => UNIVERSAL SERIAL BUS TYPE-C POWER DELIVERY [patent_app_type] => utility [patent_app_number] => 15/396527 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396527
Universal serial bus type-C power delivery Dec 30, 2016 Issued
Array ( [id] => 12892117 [patent_doc_number] => 20180189214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => CROSSTALK CANCELLATION TRANSMISSION BRIDGE [patent_app_type] => utility [patent_app_number] => 15/396268 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396268 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396268
CROSSTALK CANCELLATION TRANSMISSION BRIDGE Dec 29, 2016 Abandoned
Array ( [id] => 12892138 [patent_doc_number] => 20180189221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => POSITIONALLY AWARE COMMUNICATION WITH MULTIPLE STORAGE DEVICES OVER A MULTI-WIRE SERIAL BUS [patent_app_type] => utility [patent_app_number] => 15/395821 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395821 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395821
Positionally aware communication with multiple storage devices over a multi-wire serial bus Dec 29, 2016 Issued
Array ( [id] => 12153683 [patent_doc_number] => 20180024947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-01-25 [patent_title] => 'TECHNOLOGIES FOR A LOW-LATENCY INTERFACE TO DATA STORAGE' [patent_app_type] => utility [patent_app_number] => 15/396028 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13135 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396028 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396028
Technologies for a low-latency interface to data storage Dec 29, 2016 Issued
Array ( [id] => 14798715 [patent_doc_number] => 10402362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Management and dispatching apparatus, system, and method based on SAS [patent_app_type] => utility [patent_app_number] => 15/393681 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 8291 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15393681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/393681
Management and dispatching apparatus, system, and method based on SAS Dec 28, 2016 Issued
Array ( [id] => 12892126 [patent_doc_number] => 20180189217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => TECHNIQUES FOR AN EXTENDABLE PERIPHERAL PORT [patent_app_type] => utility [patent_app_number] => 15/394530 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15394530 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/394530
TECHNIQUES FOR AN EXTENDABLE PERIPHERAL PORT Dec 28, 2016 Abandoned
Array ( [id] => 12892129 [patent_doc_number] => 20180189218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => MEMORY DRIVE ADAPTERS AND MEMORY DRIVE UNITS INCORPORATING THE SAME [patent_app_type] => utility [patent_app_number] => 15/394709 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15394709 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/394709
Memory drive adapters and memory drive units incorporating the same Dec 28, 2016 Issued
Array ( [id] => 12869032 [patent_doc_number] => 20180181519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-28 [patent_title] => METHOD AND APPARATUS FOR ACCESSING NON-VOLATILE MEMORY AS BYTE ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 15/389811 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5758 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15389811 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/389811
Method and apparatus for accessing non-volatile memory as byte addressable memory Dec 22, 2016 Issued
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