Richard B. Franklin

Array ( [id] => 19558601 [patent_doc_number] => 20240370393 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => Management of Memory Access to Reduce Impacts of Direct Memory Access Latency [patent_app_type] => utility [patent_app_number] => 18/604318 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22093 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18604318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19419838 [patent_doc_number] => 20240295961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => MEMORY DEVICE HAVING HIDDEN REFRESH [patent_app_type] => utility [patent_app_number] => 18/598323 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4556 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598323 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19419867 [patent_doc_number] => 20240295990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => System and Method for searching a buffer of a non-volatile storage Host Controller [patent_app_type] => utility [patent_app_number] => 18/592554 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2518 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18592554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19573574 [patent_doc_number] => 20240377866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => DISPLAY CARD MODULE AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/442097 [patent_app_country] => US [patent_app_date] => 2024-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442097 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19220004 [patent_doc_number] => 20240184708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-06 [patent_title] => ACCELERATING DATA MESSAGE CLASSIFICATION WITH SMART NICS [patent_app_type] => utility [patent_app_number] => 18/437627 [patent_app_country] => US [patent_app_date] => 2024-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9313 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18437627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19190880 [patent_doc_number] => 20240169793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => METHODS AND SYSTEMS FOR PRESENTING A GAMING-RELATED MESSAGE TO A GAMER IN AN AREA PROXIMATE TO A BEACON ASSOCIATED WITH A CASINO [patent_app_type] => utility [patent_app_number] => 18/430413 [patent_app_country] => US [patent_app_date] => 2024-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18430413 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19101954 [patent_doc_number] => 20240121182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => SYSTEM AND METHOD FOR FACILITATING EFFICIENT ADDRESS TRANSLATION IN A NETWORK INTERFACE CONTROLLER (NIC) [patent_app_type] => utility [patent_app_number] => 18/545808 [patent_app_country] => US [patent_app_date] => 2023-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18545808 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19099786 [patent_doc_number] => 20240119014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-11 [patent_title] => NOVEL SSD ARCHITECTURE FOR FPGA BASED ACCELERATION [patent_app_type] => utility [patent_app_number] => 18/544415 [patent_app_country] => US [patent_app_date] => 2023-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 43773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18544415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19084894 [patent_doc_number] => 20240111695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => MEMORY DEVICE PERFORMING SELF-CALIBRATION BY IDENTIFYING LOCATION INFORMATION AND MEMORY MODULE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/538263 [patent_app_country] => US [patent_app_date] => 2023-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13149 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18538263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19334215 [patent_doc_number] => 20240248645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => MEMORY SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 18/535956 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9984 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18535956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19851940 [patent_doc_number] => 20250097291 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => Maintaining Consistent Metadata Across Different Storage Systems [patent_app_type] => utility [patent_app_number] => 18/528412 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 61573 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18528412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20000820 [patent_doc_number] => 20250139042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => CONTROL DEVICE, CONTROL METHOD AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/522879 [patent_app_country] => US [patent_app_date] => 2023-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1185 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18522879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19190553 [patent_doc_number] => 20240169466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SYSTEMS AND METHODS FOR EXPLOITING QUEUES AND TRANSITIONAL STORAGE FOR IMPROVED LOW-LATENCY HIGH-BANDWIDTH ON-DIE DATA RETRIEVAL [patent_app_type] => utility [patent_app_number] => 18/519844 [patent_app_country] => US [patent_app_date] => 2023-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 34343 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18519844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19787390 [patent_doc_number] => 20250061069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => ACCELERATOR SYSTEM AND METHOD TO EXECUTE DEPTHWISE SEPARABLE CONVOLUTION [patent_app_type] => utility [patent_app_number] => 18/509381 [patent_app_country] => US [patent_app_date] => 2023-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18509381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20529135 [patent_doc_number] => 12547571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Connection interface and lane connection method thereof adapted for die-to-die [patent_app_type] => utility [patent_app_number] => 18/386404 [patent_app_country] => US [patent_app_date] => 2023-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3420 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18386404 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20000684 [patent_doc_number] => 20250138906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => DEADLOCK PREVENTION UTILIZING DISTRIBUTED RESOURCE RESERVATIONS [patent_app_type] => utility [patent_app_number] => 18/385973 [patent_app_country] => US [patent_app_date] => 2023-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18385973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19979133 [patent_doc_number] => 12346608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Asynchronous arbitration across clock domains for register writes in an integrated circuit chip [patent_app_type] => utility [patent_app_number] => 18/497888 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19979133 [patent_doc_number] => 12346608 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Asynchronous arbitration across clock domains for register writes in an integrated circuit chip [patent_app_type] => utility [patent_app_number] => 18/497888 [patent_app_country] => US [patent_app_date] => 2023-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18497888 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19545137 [patent_doc_number] => 20240362173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => HYBRID MICROPROCESSOR AND PROGRAMMABLE LOGIC DEVICE (PLD)-BASED ARCHITECTURE INCLUDING INTER PROCESSOR COMMUNICATION [patent_app_type] => utility [patent_app_number] => 18/475829 [patent_app_country] => US [patent_app_date] => 2023-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18475829 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19021873 [patent_doc_number] => 20240078044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => VARIABLE MEMORY ACCESS GRANULARITY [patent_app_type] => utility [patent_app_number] => 18/371300 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6266 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18371300 [rel_patent_id] =>[rel_patent_doc_number] =>)