
Richard E. Chilcot
Examiner (ID: 17474, Phone: (571)272-6777 , Office: P/2916 )
| Most Active Art Unit | 2916 |
| Art Unit(s) | 3635, 2616, 1804, 3627, 2167, 3634, 2214, 3621, 2855, 3504, 2899, 2910, 2916 |
| Total Applications | 3224 |
| Issued Applications | 2808 |
| Pending Applications | 24 |
| Abandoned Applications | 392 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8522781
[patent_doc_number] => 20120322189
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-12-20
[patent_title] => 'METHOD FOR PRODUCING A GROUP III NITRIDE SEMICONDUCTOR LIGHT-EMITTING DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/525110
[patent_app_country] => US
[patent_app_date] => 2012-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3224
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13525110
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/525110 | Method for producing a group III nitride semiconductor light-emitting device | Jun 14, 2012 | Issued |
Array
(
[id] => 9455083
[patent_doc_number] => 08716090
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-06
[patent_title] => 'Semiconductor device manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 13/580962
[patent_app_country] => US
[patent_app_date] => 2012-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 3437
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13580962
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/580962 | Semiconductor device manufacturing method | Jun 11, 2012 | Issued |
Array
(
[id] => 10118865
[patent_doc_number] => 09153758
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-10-06
[patent_title] => 'Method of attaching a light emitting device to a support substrate'
[patent_app_type] => utility
[patent_app_number] => 14/118564
[patent_app_country] => US
[patent_app_date] => 2012-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 10
[patent_no_of_words] => 5966
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14118564
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/118564 | Method of attaching a light emitting device to a support substrate | May 20, 2012 | Issued |
Array
(
[id] => 8495974
[patent_doc_number] => 20120295382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-22
[patent_title] => 'METHOD OF LIFT-OFF PATTERNING THIN FILMS IN SITU EMPLOYING PHASE CHANGE RESISTS'
[patent_app_type] => utility
[patent_app_number] => 13/465065
[patent_app_country] => US
[patent_app_date] => 2012-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 8949
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13465065
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/465065 | Method of lift-off patterning thin films in situ employing phase change resists | May 6, 2012 | Issued |
Array
(
[id] => 9132065
[patent_doc_number] => 20130292778
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-07
[patent_title] => 'Techniques for the Fabrication of Thick Gate Dielectric'
[patent_app_type] => utility
[patent_app_number] => 13/464966
[patent_app_country] => US
[patent_app_date] => 2012-05-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3646
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464966
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/464966 | Techniques for the fabrication of thick gate dielectric | May 4, 2012 | Issued |
Array
(
[id] => 8480806
[patent_doc_number] => 20120280213
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-08
[patent_title] => 'Method of Fabricating Thin Film Transistor and Top-gate Type Thin Film Transistor'
[patent_app_type] => utility
[patent_app_number] => 13/463856
[patent_app_country] => US
[patent_app_date] => 2012-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4765
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463856
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/463856 | Method of Fabricating Thin Film Transistor and Top-gate Type Thin Film Transistor | May 3, 2012 | Abandoned |
Array
(
[id] => 9135020
[patent_doc_number] => 20130295735
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-11-07
[patent_title] => 'SEMICONDUCTOR PROCESS'
[patent_app_type] => utility
[patent_app_number] => 13/463819
[patent_app_country] => US
[patent_app_date] => 2012-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3440
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463819
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/463819 | Semiconductor process | May 3, 2012 | Issued |
Array
(
[id] => 10888021
[patent_doc_number] => 08912017
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-12-16
[patent_title] => 'Semiconductor wafer bonding incorporating electrical and optical interconnects'
[patent_app_type] => utility
[patent_app_number] => 13/463130
[patent_app_country] => US
[patent_app_date] => 2012-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 9
[patent_no_of_words] => 15925
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463130
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/463130 | Semiconductor wafer bonding incorporating electrical and optical interconnects | May 2, 2012 | Issued |
Array
(
[id] => 8904294
[patent_doc_number] => 20130171797
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-07-04
[patent_title] => 'METHOD FOR FORMING MULTI-COMPONENT LAYER, METHOD FOR FORMING MULTI-COMPONENT DIELECTRIC LAYER AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/463215
[patent_app_country] => US
[patent_app_date] => 2012-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6409
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463215
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/463215 | METHOD FOR FORMING MULTI-COMPONENT LAYER, METHOD FOR FORMING MULTI-COMPONENT DIELECTRIC LAYER AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE | May 2, 2012 | Abandoned |
Array
(
[id] => 9648525
[patent_doc_number] => 08802535
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-12
[patent_title] => 'Doped core trigate FET structure and method'
[patent_app_type] => utility
[patent_app_number] => 13/461935
[patent_app_country] => US
[patent_app_date] => 2012-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 28
[patent_no_of_words] => 5401
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461935
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/461935 | Doped core trigate FET structure and method | May 1, 2012 | Issued |
Array
(
[id] => 8480828
[patent_doc_number] => 20120280235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-08
[patent_title] => 'THIN FILM FET DEVICE AND METHOD FOR FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 13/461905
[patent_app_country] => US
[patent_app_date] => 2012-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4416
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461905
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/461905 | THIN FILM FET DEVICE AND METHOD FOR FORMING THE SAME | May 1, 2012 | Abandoned |
Array
(
[id] => 8821565
[patent_doc_number] => 20130122610
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-16
[patent_title] => 'Apparatus and Method for Die Bonding'
[patent_app_type] => utility
[patent_app_number] => 13/460901
[patent_app_country] => US
[patent_app_date] => 2012-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6704
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460901
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/460901 | Apparatus and Method for Die Bonding | Apr 30, 2012 | Abandoned |
Array
(
[id] => 9648553
[patent_doc_number] => 08802564
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-12
[patent_title] => 'Method of manufacturing a semiconductor component'
[patent_app_type] => utility
[patent_app_number] => 13/460939
[patent_app_country] => US
[patent_app_date] => 2012-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 683
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13460939
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/460939 | Method of manufacturing a semiconductor component | Apr 30, 2012 | Issued |
Array
(
[id] => 9140184
[patent_doc_number] => 08580644
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-11-12
[patent_title] => 'Multi-level lateral floating coupled capacitor transistor structures'
[patent_app_type] => utility
[patent_app_number] => 13/461646
[patent_app_country] => US
[patent_app_date] => 2012-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 8236
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13461646
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/461646 | Multi-level lateral floating coupled capacitor transistor structures | Apr 30, 2012 | Issued |
Array
(
[id] => 9648454
[patent_doc_number] => 08802464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-08-12
[patent_title] => 'Method of forming process substrate using thin glass substrate and method of fabricating flat display device using the same'
[patent_app_type] => utility
[patent_app_number] => 13/459781
[patent_app_country] => US
[patent_app_date] => 2012-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 14
[patent_no_of_words] => 7567
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459781
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/459781 | Method of forming process substrate using thin glass substrate and method of fabricating flat display device using the same | Apr 29, 2012 | Issued |
Array
(
[id] => 9121526
[patent_doc_number] => 20130288448
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-31
[patent_title] => 'SEMICONDUCTOR PROCESS'
[patent_app_type] => utility
[patent_app_number] => 13/459262
[patent_app_country] => US
[patent_app_date] => 2012-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3550
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459262
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/459262 | Semiconductor process | Apr 29, 2012 | Issued |
Array
(
[id] => 8477315
[patent_doc_number] => 20120276721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-01
[patent_title] => 'METHOD OF FORMING AN OXIDE LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE INCLUDING THE OXIDE LAYER'
[patent_app_type] => utility
[patent_app_number] => 13/459136
[patent_app_country] => US
[patent_app_date] => 2012-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 25
[patent_no_of_words] => 17275
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459136
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/459136 | Method of forming an oxide layer and method of manufacturing semiconductor device including the oxide layer | Apr 27, 2012 | Issued |
Array
(
[id] => 8477290
[patent_doc_number] => 20120276697
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-01
[patent_title] => 'MANUFACTURING METHOD OF ARRAY SUBSTRATE'
[patent_app_type] => utility
[patent_app_number] => 13/458478
[patent_app_country] => US
[patent_app_date] => 2012-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5305
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458478
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/458478 | Manufacturing method of array substrate | Apr 26, 2012 | Issued |
Array
(
[id] => 8955866
[patent_doc_number] => 08501638
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-08-06
[patent_title] => 'Laser annealing scanning methods with reduced annealing non-uniformities'
[patent_app_type] => utility
[patent_app_number] => 13/459031
[patent_app_country] => US
[patent_app_date] => 2012-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 3717
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13459031
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/459031 | Laser annealing scanning methods with reduced annealing non-uniformities | Apr 26, 2012 | Issued |
Array
(
[id] => 9370417
[patent_doc_number] => 20140080290
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-20
[patent_title] => 'METHOD OF SELECTIVE GROWTH WITHOUT CATALYST ON A SEMICONDUCTING STRUCTURE'
[patent_app_type] => utility
[patent_app_number] => 14/009305
[patent_app_country] => US
[patent_app_date] => 2012-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6864
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14009305
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/009305 | Method of selective growth without catalyst on a semiconducting structure | Apr 2, 2012 | Issued |