Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11525243 [patent_doc_number] => 09608662 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'Apparatus and method for converting floating-point operand into a value having a different format' [patent_app_type] => utility [patent_app_number] => 14/498118 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7138 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14498118 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/498118
Apparatus and method for converting floating-point operand into a value having a different format Sep 25, 2014 Issued
Array ( [id] => 11320717 [patent_doc_number] => 09519460 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-13 [patent_title] => 'Universal single instruction multiple data multiplier and wide accumulator unit' [patent_app_type] => utility [patent_app_number] => 14/496426 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5425 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496426 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/496426
Universal single instruction multiple data multiplier and wide accumulator unit Sep 24, 2014 Issued
Array ( [id] => 11245236 [patent_doc_number] => 09471278 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-18 [patent_title] => 'Low area full adder with shared transistors' [patent_app_type] => utility [patent_app_number] => 14/496767 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6029 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496767 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/496767
Low area full adder with shared transistors Sep 24, 2014 Issued
Array ( [id] => 11390944 [patent_doc_number] => 09552189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-24 [patent_title] => 'Embedded floating-point operator circuitry' [patent_app_type] => utility [patent_app_number] => 14/497250 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9926 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14497250 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/497250
Embedded floating-point operator circuitry Sep 24, 2014 Issued
Array ( [id] => 10203966 [patent_doc_number] => 20150088953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'METHODS, SYSTEMS AND COMPUTER-READABLE MEDIA FOR DISTRIBUTED PROBABILISTIC MATRIX FACTORIZATION' [patent_app_type] => utility [patent_app_number] => 14/493308 [patent_app_country] => US [patent_app_date] => 2014-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6265 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14493308 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/493308
METHODS, SYSTEMS AND COMPUTER-READABLE MEDIA FOR DISTRIBUTED PROBABILISTIC MATRIX FACTORIZATION Sep 21, 2014 Abandoned
Array ( [id] => 10203964 [patent_doc_number] => 20150088952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'ARITHMETIC PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/492782 [patent_app_country] => US [patent_app_date] => 2014-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 18927 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14492782 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/492782
ARITHMETIC PROCESSING DEVICE Sep 21, 2014 Abandoned
Array ( [id] => 11392335 [patent_doc_number] => 09553591 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-24 [patent_title] => 'Hybrid architecture for signal processing' [patent_app_type] => utility [patent_app_number] => 14/492717 [patent_app_country] => US [patent_app_date] => 2014-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6164 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14492717 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/492717
Hybrid architecture for signal processing Sep 21, 2014 Issued
Array ( [id] => 10741452 [patent_doc_number] => 20160087604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'DIGITAL COMPENSATION FOR A NON-LINEAR ANALOG RECEIVER' [patent_app_type] => utility [patent_app_number] => 14/492180 [patent_app_country] => US [patent_app_date] => 2014-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13967 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14492180 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/492180
Digital compensation for a non-linear analog receiver Sep 21, 2014 Issued
Array ( [id] => 10921916 [patent_doc_number] => 20140324935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'MATRIX COMPUTATION FRAMEWORK' [patent_app_type] => utility [patent_app_number] => 14/329591 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329591 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329591
MATRIX COMPUTATION FRAMEWORK Jul 10, 2014 Abandoned
Array ( [id] => 10493660 [patent_doc_number] => 20150378682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'EFFICIENT CONSTANT MULTIPLIER IMPLEMENTATION FOR PROGRAMMABLE LOGIC DEVICES' [patent_app_type] => utility [patent_app_number] => 14/316049 [patent_app_country] => US [patent_app_date] => 2014-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6310 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14316049 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/316049
Efficient constant multiplier implementation for programmable logic devices Jun 25, 2014 Issued
Array ( [id] => 11812155 [patent_doc_number] => 09716734 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'System and method for long range and short range data compression' [patent_app_type] => utility [patent_app_number] => 14/301295 [patent_app_country] => US [patent_app_date] => 2014-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 13858 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14301295 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/301295
System and method for long range and short range data compression Jun 9, 2014 Issued
Array ( [id] => 9758596 [patent_doc_number] => 20140289296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-25 [patent_title] => 'SYSTEM AND METHOD OF GENERATING COMPLEX WAVEFORMS' [patent_app_type] => utility [patent_app_number] => 14/299123 [patent_app_country] => US [patent_app_date] => 2014-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10718 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14299123 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/299123
SYSTEM AND METHOD OF GENERATING COMPLEX WAVEFORMS Jun 8, 2014 Abandoned
Array ( [id] => 11013194 [patent_doc_number] => 20160210146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'Vector Operation Core and Vector Processor' [patent_app_type] => utility [patent_app_number] => 15/023617 [patent_app_country] => US [patent_app_date] => 2014-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6962 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15023617 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/023617
Vector operation core and vector processor May 19, 2014 Issued
Array ( [id] => 11345184 [patent_doc_number] => 09529590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-27 [patent_title] => 'Processor for large graph algorithm computations and matrix operations' [patent_app_type] => utility [patent_app_number] => 14/281132 [patent_app_country] => US [patent_app_date] => 2014-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 15630 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14281132 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/281132
Processor for large graph algorithm computations and matrix operations May 18, 2014 Issued
Array ( [id] => 11285407 [patent_doc_number] => 09501261 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-22 [patent_title] => 'Binary array with LSB dithering in a closed loop system' [patent_app_type] => utility [patent_app_number] => 14/271402 [patent_app_country] => US [patent_app_date] => 2014-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6742 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14271402 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/271402
Binary array with LSB dithering in a closed loop system May 5, 2014 Issued
Array ( [id] => 11465841 [patent_doc_number] => 09582473 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-28 [patent_title] => 'Instruction set to enable efficient implementation of fixed point fast fourier transform (FFT) algorithms' [patent_app_type] => utility [patent_app_number] => 14/267789 [patent_app_country] => US [patent_app_date] => 2014-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4189 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14267789 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/267789
Instruction set to enable efficient implementation of fixed point fast fourier transform (FFT) algorithms Apr 30, 2014 Issued
Array ( [id] => 11431087 [patent_doc_number] => 09569405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Generating correlation scores' [patent_app_type] => utility [patent_app_number] => 14/265868 [patent_app_country] => US [patent_app_date] => 2014-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 15148 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 456 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14265868 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/265868
Generating correlation scores Apr 29, 2014 Issued
Array ( [id] => 10941300 [patent_doc_number] => 20140344321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-20 [patent_title] => 'AUTOMATIC CONTROL SYSTEM AND METHOD FOR A TRUE RANDOM NUMBER GENERATOR' [patent_app_type] => utility [patent_app_number] => 14/259661 [patent_app_country] => US [patent_app_date] => 2014-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5440 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14259661 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/259661
Automatic control system and method for a true random number generator Apr 22, 2014 Issued
Array ( [id] => 11846575 [patent_doc_number] => 09734129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Low complexity partial parallel architectures for Fourier transform and inverse Fourier transform over subfields of a finite field' [patent_app_type] => utility [patent_app_number] => 14/258679 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 13149 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258679 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258679
Low complexity partial parallel architectures for Fourier transform and inverse Fourier transform over subfields of a finite field Apr 21, 2014 Issued
Array ( [id] => 11306473 [patent_doc_number] => 09513870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Modulo9 and modulo7 operation on unsigned binary numbers' [patent_app_type] => utility [patent_app_number] => 14/258664 [patent_app_country] => US [patent_app_date] => 2014-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8087 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14258664 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/258664
Modulo9 and modulo7 operation on unsigned binary numbers Apr 21, 2014 Issued
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