Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10872995 [patent_doc_number] => 08898213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Apparatus and method for division of a Galois field binary polynomial' [patent_app_type] => utility [patent_app_number] => 13/324322 [patent_app_country] => US [patent_app_date] => 2011-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9755 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13324322 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/324322
Apparatus and method for division of a Galois field binary polynomial Dec 12, 2011 Issued
Array ( [id] => 9458299 [patent_doc_number] => 08719321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Adaptive block-size transform using LLMICT' [patent_app_type] => utility [patent_app_number] => 13/316556 [patent_app_country] => US [patent_app_date] => 2011-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3340 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13316556 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/316556
Adaptive block-size transform using LLMICT Dec 10, 2011 Issued
Array ( [id] => 10840935 [patent_doc_number] => 08868634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-21 [patent_title] => 'Method and apparatus for performing multiplication in a processor' [patent_app_type] => utility [patent_app_number] => 13/309721 [patent_app_country] => US [patent_app_date] => 2011-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 7712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13309721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/309721
Method and apparatus for performing multiplication in a processor Dec 1, 2011 Issued
Array ( [id] => 8267078 [patent_doc_number] => 20120166508 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'FAST FOURIER TRANSFORMER' [patent_app_type] => utility [patent_app_number] => 13/305450 [patent_app_country] => US [patent_app_date] => 2011-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2346 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13305450 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/305450
FAST FOURIER TRANSFORMER Nov 27, 2011 Abandoned
Array ( [id] => 9714068 [patent_doc_number] => 08838665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Fast condition code generation for arithmetic logic unit' [patent_app_type] => utility [patent_app_number] => 13/296087 [patent_app_country] => US [patent_app_date] => 2011-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9438 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13296087 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/296087
Fast condition code generation for arithmetic logic unit Nov 13, 2011 Issued
Array ( [id] => 9578555 [patent_doc_number] => 08768990 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Reconfigurable cyclic shifter arrangement' [patent_app_type] => utility [patent_app_number] => 13/294332 [patent_app_country] => US [patent_app_date] => 2011-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 8511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13294332 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/294332
Reconfigurable cyclic shifter arrangement Nov 10, 2011 Issued
Array ( [id] => 8346267 [patent_doc_number] => 20120207200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'REDUCING STEADY STATE ERROR IN FIXED POINT IMPLEMENTATIONS OF RECURSIVE FILTERS' [patent_app_type] => utility [patent_app_number] => 13/293498 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6695 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13293498 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/293498
Reducing steady state error in fixed point implementations or recursive filters Nov 9, 2011 Issued
Array ( [id] => 8929584 [patent_doc_number] => 20130185344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => 'MODIFIED GABOR TRANSFORM WITH GAUSSIAN COMPRESSION AND BI-ORTHOGONAL DIRICHLET GAUSSIAN DECOMPRESSION' [patent_app_type] => utility [patent_app_number] => 13/822297 [patent_app_country] => US [patent_app_date] => 2011-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10361 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13822297 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/822297
MODIFIED GABOR TRANSFORM WITH GAUSSIAN COMPRESSION AND BI-ORTHOGONAL DIRICHLET GAUSSIAN DECOMPRESSION Oct 31, 2011 Abandoned
Array ( [id] => 9506784 [patent_doc_number] => 08745112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Electronic calculator, calculation result displaying method, and recording medium storing program for displaying calculation result' [patent_app_type] => utility [patent_app_number] => 13/270430 [patent_app_country] => US [patent_app_date] => 2011-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 5177 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13270430 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/270430
Electronic calculator, calculation result displaying method, and recording medium storing program for displaying calculation result Oct 10, 2011 Issued
Array ( [id] => 9695104 [patent_doc_number] => 08825730 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-02 [patent_title] => 'Matrix decomposition using dataflow techniques' [patent_app_type] => utility [patent_app_number] => 13/252562 [patent_app_country] => US [patent_app_date] => 2011-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8254 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13252562 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/252562
Matrix decomposition using dataflow techniques Oct 3, 2011 Issued
Array ( [id] => 8735171 [patent_doc_number] => 20130080740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'FAST CONDITION CODE GENERATION FOR ARITHMETIC LOGIC UNIT' [patent_app_type] => utility [patent_app_number] => 13/247796 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9360 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247796 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/247796
Fast condition code generation for arithmetic logic unit Sep 27, 2011 Issued
Array ( [id] => 8314740 [patent_doc_number] => 20120191766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'Multiplication of Complex Numbers Represented in Floating Point' [patent_app_type] => utility [patent_app_number] => 13/247214 [patent_app_country] => US [patent_app_date] => 2011-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3261 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13247214 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/247214
Multiplication of Complex Numbers Represented in Floating Point Sep 27, 2011 Abandoned
Array ( [id] => 8143039 [patent_doc_number] => 20120096062 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'MODULAR CALCULATOR, OPERATION METHOD OF THE MODULAR CALCULATOR, AND APPARATUSES HAVING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/241778 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10930 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096062.pdf [firstpage_image] =>[orig_patent_app_number] => 13241778 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/241778
Modular calculator, operation method of the modular calculator, and apparatuses having the same Sep 22, 2011 Issued
Array ( [id] => 9071396 [patent_doc_number] => 20130263152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'SYSTEM FOR SCHEDULING THE EXECUTION OF TASKS BASED ON LOGICAL TIME VECTORS' [patent_app_type] => utility [patent_app_number] => 13/824467 [patent_app_country] => US [patent_app_date] => 2011-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7032 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13824467 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/824467
SYSTEM FOR SCHEDULING THE EXECUTION OF TASKS BASED ON LOGICAL TIME VECTORS Sep 20, 2011 Abandoned
Array ( [id] => 9592548 [patent_doc_number] => 08782109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Asynchronous sample rate conversion using a polynomial interpolator with minimax stopband attenuation' [patent_app_type] => utility [patent_app_number] => 13/228679 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 28 [patent_no_of_words] => 6671 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13228679 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/228679
Asynchronous sample rate conversion using a polynomial interpolator with minimax stopband attenuation Sep 8, 2011 Issued
Array ( [id] => 9430709 [patent_doc_number] => 08706794 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-22 [patent_title] => 'No-multiply digital signal processing method' [patent_app_type] => utility [patent_app_number] => 13/216030 [patent_app_country] => US [patent_app_date] => 2011-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4710 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13216030 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/216030
No-multiply digital signal processing method Aug 22, 2011 Issued
Array ( [id] => 7819662 [patent_doc_number] => 20120066282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'Whole 1 number method of integer factorization' [patent_app_type] => utility [patent_app_number] => 13/190646 [patent_app_country] => US [patent_app_date] => 2011-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1105 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0066/20120066282.pdf [firstpage_image] =>[orig_patent_app_number] => 13190646 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/190646
Whole 1 number method of integer factorization Jul 25, 2011 Abandoned
Array ( [id] => 8619178 [patent_doc_number] => 20130024490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'RANDOM NUMBER GENERATOR' [patent_app_type] => utility [patent_app_number] => 13/187763 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7941 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13187763 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/187763
Random number generator Jul 20, 2011 Issued
Array ( [id] => 10052504 [patent_doc_number] => 09092384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Quantifying method for intrinsic data transfer rate of algorithms' [patent_app_type] => utility [patent_app_number] => 13/700336 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5000 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13700336 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/700336
Quantifying method for intrinsic data transfer rate of algorithms Jul 19, 2011 Issued
Array ( [id] => 8619177 [patent_doc_number] => 20130024489 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-24 [patent_title] => 'METHOD FOR FAST CALCULATION OF THE BEGINNING OF PSEUDO RANDOM SEQUENCES FOR LONG TERM EVOLUTION' [patent_app_type] => utility [patent_app_number] => 13/184646 [patent_app_country] => US [patent_app_date] => 2011-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13184646 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/184646
Method for fast calculation of the beginning of pseudo random sequences for long term evolution Jul 17, 2011 Issued
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