Richard L Schilling
Examiner (ID: 9849)
Most Active Art Unit | 1506 |
Art Unit(s) | 1506, 1752, 1302, 1795, 1715, 1113 |
Total Applications | 3259 |
Issued Applications | 2786 |
Pending Applications | 25 |
Abandoned Applications | 448 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4526586
[patent_doc_number] => 07933942
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-26
[patent_title] => 'Low cost, high purity sign wave generator'
[patent_app_type] => utility
[patent_app_number] => 11/540810
[patent_app_country] => US
[patent_app_date] => 2006-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 11375
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/933/07933942.pdf
[firstpage_image] =>[orig_patent_app_number] => 11540810
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/540810 | Low cost, high purity sign wave generator | Sep 28, 2006 | Issued |
Array
(
[id] => 7798237
[patent_doc_number] => 08126955
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-02-28
[patent_title] => 'N bit adder and the corresponding adding method'
[patent_app_type] => utility
[patent_app_number] => 12/066638
[patent_app_country] => US
[patent_app_date] => 2006-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8309
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/126/08126955.pdf
[firstpage_image] =>[orig_patent_app_number] => 12066638
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/066638 | N bit adder and the corresponding adding method | Sep 5, 2006 | Issued |
Array
(
[id] => 4665258
[patent_doc_number] => 20080256165
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-10-16
[patent_title] => 'Full-Adder Modules and Multiplier Devices Using the Same'
[patent_app_type] => utility
[patent_app_number] => 12/065633
[patent_app_country] => US
[patent_app_date] => 2006-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3480
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0256/20080256165.pdf
[firstpage_image] =>[orig_patent_app_number] => 12065633
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/065633 | Full-Adder Modules and Multiplier Devices Using the Same | Sep 3, 2006 | Abandoned |
Array
(
[id] => 5091055
[patent_doc_number] => 20070230694
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-10-04
[patent_title] => 'Cryptographically secure pseudo-random number generator'
[patent_app_type] => utility
[patent_app_number] => 11/509215
[patent_app_country] => US
[patent_app_date] => 2006-08-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7325
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 35
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0230/20070230694.pdf
[firstpage_image] =>[orig_patent_app_number] => 11509215
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/509215 | Cryptographically secure pseudo-random number generator | Aug 22, 2006 | Issued |
Array
(
[id] => 4829384
[patent_doc_number] => 20080126454
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-05-29
[patent_title] => 'Selectively attachable calculator'
[patent_app_type] => utility
[patent_app_number] => 11/465889
[patent_app_country] => US
[patent_app_date] => 2006-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2200
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0126/20080126454.pdf
[firstpage_image] =>[orig_patent_app_number] => 11465889
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/465889 | Selectively attachable calculator | Aug 20, 2006 | Issued |
Array
(
[id] => 4917454
[patent_doc_number] => 20080098055
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-04-24
[patent_title] => 'PROBABILITY DENSITY FUNCTION SEPARATING APPARATUS, PROBABILITY DENSITY FUNCTION SEPARATING METHOD, TESTING APPARATUS, BIT ERROR RATE MEASURING APPARATUS, ELECTRONIC DEVICE, AND PROGRAM'
[patent_app_type] => utility
[patent_app_number] => 11/463644
[patent_app_country] => US
[patent_app_date] => 2006-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 45
[patent_no_of_words] => 21804
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0098/20080098055.pdf
[firstpage_image] =>[orig_patent_app_number] => 11463644
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/463644 | Probability density function separating apparatus, probability density function separating method, testing apparatus, bit error rate measuring apparatus, electronic device, and program | Aug 9, 2006 | Issued |
Array
(
[id] => 5155810
[patent_doc_number] => 20070038693
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-02-15
[patent_title] => 'Method and Processor for Performing a Floating-Point Instruction Within a Processor'
[patent_app_type] => utility
[patent_app_number] => 11/462069
[patent_app_country] => US
[patent_app_date] => 2006-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4498
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0038/20070038693.pdf
[firstpage_image] =>[orig_patent_app_number] => 11462069
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/462069 | Method and Processor for Performing a Floating-Point Instruction Within a Processor | Aug 2, 2006 | Abandoned |
Array
(
[id] => 5734413
[patent_doc_number] => 20060259530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-11-16
[patent_title] => 'DECIMAL MULTIPLICATION FOR SUPERSCALER PROCESSORS'
[patent_app_type] => utility
[patent_app_number] => 11/460296
[patent_app_country] => US
[patent_app_date] => 2006-07-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5755
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0259/20060259530.pdf
[firstpage_image] =>[orig_patent_app_number] => 11460296
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/460296 | Decimal multiplication for superscaler processors | Jul 26, 2006 | Issued |
Array
(
[id] => 8580601
[patent_doc_number] => 08346831
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-01-01
[patent_title] => 'Systems and methods for computing mathematical functions'
[patent_app_type] => utility
[patent_app_number] => 11/493714
[patent_app_country] => US
[patent_app_date] => 2006-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1897
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11493714
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/493714 | Systems and methods for computing mathematical functions | Jul 24, 2006 | Issued |
Array
(
[id] => 4548340
[patent_doc_number] => 07873687
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-01-18
[patent_title] => 'Method for calculating a result of a division with a floating point unit with fused multiply-add'
[patent_app_type] => utility
[patent_app_number] => 11/458405
[patent_app_country] => US
[patent_app_date] => 2006-07-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1694
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/873/07873687.pdf
[firstpage_image] =>[orig_patent_app_number] => 11458405
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/458405 | Method for calculating a result of a division with a floating point unit with fused multiply-add | Jul 18, 2006 | Issued |
Array
(
[id] => 4591625
[patent_doc_number] => 07836117
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-11-16
[patent_title] => 'Specialized processing block for programmable logic device'
[patent_app_type] => utility
[patent_app_number] => 11/458361
[patent_app_country] => US
[patent_app_date] => 2006-07-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 4489
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/836/07836117.pdf
[firstpage_image] =>[orig_patent_app_number] => 11458361
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/458361 | Specialized processing block for programmable logic device | Jul 17, 2006 | Issued |
Array
(
[id] => 37904
[patent_doc_number] => 07788306
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-08-31
[patent_title] => 'On-demand numerical conversion'
[patent_app_type] => utility
[patent_app_number] => 11/457290
[patent_app_country] => US
[patent_app_date] => 2006-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4998
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/788/07788306.pdf
[firstpage_image] =>[orig_patent_app_number] => 11457290
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/457290 | On-demand numerical conversion | Jul 12, 2006 | Issued |
Array
(
[id] => 4798746
[patent_doc_number] => 20080010332
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-10
[patent_title] => 'EFFICIENT COMPUTATION OF THE MODULO OPERATION BASED ON DIVISOR (2n-1)'
[patent_app_type] => utility
[patent_app_number] => 11/456110
[patent_app_country] => US
[patent_app_date] => 2006-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9072
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0010/20080010332.pdf
[firstpage_image] =>[orig_patent_app_number] => 11456110
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/456110 | Efficient computation of the modulo operation based on divisor (2n-1) | Jul 6, 2006 | Issued |
Array
(
[id] => 5689753
[patent_doc_number] => 20060288068
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-21
[patent_title] => 'Memory control method for storing operational result data with the data order changed for further operation'
[patent_app_type] => utility
[patent_app_number] => 11/454863
[patent_app_country] => US
[patent_app_date] => 2006-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 10024
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0288/20060288068.pdf
[firstpage_image] =>[orig_patent_app_number] => 11454863
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/454863 | Memory control method for storing operational result data with the data order changed for further operation | Jun 18, 2006 | Issued |
Array
(
[id] => 4591636
[patent_doc_number] => 07836118
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-11-16
[patent_title] => 'Hardware/software-based mapping of CTAs to matrix tiles for efficient matrix multiplication'
[patent_app_type] => utility
[patent_app_number] => 11/454499
[patent_app_country] => US
[patent_app_date] => 2006-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 22
[patent_no_of_words] => 11757
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/836/07836118.pdf
[firstpage_image] =>[orig_patent_app_number] => 11454499
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/454499 | Hardware/software-based mapping of CTAs to matrix tiles for efficient matrix multiplication | Jun 15, 2006 | Issued |
Array
(
[id] => 597598
[patent_doc_number] => 07451169
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-11-11
[patent_title] => 'Method and apparatus for providing packed shift operations in a processor'
[patent_app_type] => utility
[patent_app_number] => 11/454749
[patent_app_country] => US
[patent_app_date] => 2006-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 20
[patent_no_of_words] => 13370
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/451/07451169.pdf
[firstpage_image] =>[orig_patent_app_number] => 11454749
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/454749 | Method and apparatus for providing packed shift operations in a processor | Jun 14, 2006 | Issued |
Array
(
[id] => 4591622
[patent_doc_number] => 07836116
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-11-16
[patent_title] => 'Fast fourier transforms and related transforms using cooperative thread arrays'
[patent_app_type] => utility
[patent_app_number] => 11/424511
[patent_app_country] => US
[patent_app_date] => 2006-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 14985
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/836/07836116.pdf
[firstpage_image] =>[orig_patent_app_number] => 11424511
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/424511 | Fast fourier transforms and related transforms using cooperative thread arrays | Jun 14, 2006 | Issued |
Array
(
[id] => 200572
[patent_doc_number] => 07640284
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2009-12-29
[patent_title] => 'Bit reversal methods for a parallel processor'
[patent_app_type] => utility
[patent_app_number] => 11/424514
[patent_app_country] => US
[patent_app_date] => 2006-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 15062
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/640/07640284.pdf
[firstpage_image] =>[orig_patent_app_number] => 11424514
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/424514 | Bit reversal methods for a parallel processor | Jun 14, 2006 | Issued |
Array
(
[id] => 5399527
[patent_doc_number] => 20090319590
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-24
[patent_title] => 'Method and device for generating a psuedorandom sequence'
[patent_app_type] => utility
[patent_app_number] => 11/922382
[patent_app_country] => US
[patent_app_date] => 2006-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3703
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0319/20090319590.pdf
[firstpage_image] =>[orig_patent_app_number] => 11922382
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/922382 | Method and device for generating a pseudorandom sequence | Jun 12, 2006 | Issued |
Array
(
[id] => 116094
[patent_doc_number] => 07720896
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-18
[patent_title] => 'Method and apparatus for post-processing a raw bit sequence of a noise source'
[patent_app_type] => utility
[patent_app_number] => 11/422296
[patent_app_country] => US
[patent_app_date] => 2006-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 7574
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 44
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/720/07720896.pdf
[firstpage_image] =>[orig_patent_app_number] => 11422296
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/422296 | Method and apparatus for post-processing a raw bit sequence of a noise source | Jun 4, 2006 | Issued |