Richard L Schilling
Examiner (ID: 9849)
Most Active Art Unit | 1506 |
Art Unit(s) | 1506, 1752, 1302, 1795, 1715, 1113 |
Total Applications | 3259 |
Issued Applications | 2786 |
Pending Applications | 25 |
Abandoned Applications | 448 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 192790
[patent_doc_number] => 07644116
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[patent_kind] => B2
[patent_issue_date] => 2010-01-05
[patent_title] => 'Digital implementation of fractional exponentiation'
[patent_app_type] => utility
[patent_app_number] => 11/421425
[patent_app_country] => US
[patent_app_date] => 2006-05-31
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[pdf_file] => patents/07/644/07644116.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/421425 | Digital implementation of fractional exponentiation | May 30, 2006 | Issued |
Array
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[patent_doc_number] => 20070277628
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[patent_kind] => A1
[patent_issue_date] => 2007-12-06
[patent_title] => 'Systems and methods for electronic dive table planner'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/444144 | Systems and methods for electronic dive table planner | May 30, 2006 | Abandoned |
Array
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[patent_title] => 'Reconfigurable circuit'
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Array
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[patent_issue_date] => 2007-09-20
[patent_title] => 'Method for fast quotient guess and congruencies manipulation'
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[patent_app_date] => 2006-05-30
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Array
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[patent_title] => 'Digital signal processing block having a wide multiplexer'
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Array
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[patent_title] => 'Digital signal processing circuit having a pattern circuit for determining termination conditions'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/432355 | Split-radix FFT/IFFT processor | May 11, 2006 | Abandoned |
Array
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[patent_issue_date] => 2006-10-12
[patent_title] => 'Architectural floorplan for a digital signal processing circuit'
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[patent_app_number] => 11/433369
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Array
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[id] => 4580085
[patent_doc_number] => 07840630
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[patent_title] => 'Arithmetic logic unit circuit'
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Array
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[id] => 7532420
[patent_doc_number] => 07844653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-30
[patent_title] => 'Digital signal processing circuit having a pre-adder circuit'
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Array
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[patent_title] => 'Digital signal processing circuit having input register blocks'
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Array
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Array
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Array
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Array
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