Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5650801 [patent_doc_number] => 20060136536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Data processing apparatus and method for converting a fixed point number to a floating point number' [patent_app_type] => utility [patent_app_number] => 11/019097 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7772 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20060136536.pdf [firstpage_image] =>[orig_patent_app_number] => 11019097 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019097
Data processing apparatus and method for converting a fixed point number to a floating point number Dec 21, 2004 Issued
Array ( [id] => 332679 [patent_doc_number] => 07512648 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Division algorithm' [patent_app_type] => utility [patent_app_number] => 11/020983 [patent_app_country] => US [patent_app_date] => 2004-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5308 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/512/07512648.pdf [firstpage_image] =>[orig_patent_app_number] => 11020983 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/020983
Division algorithm Dec 21, 2004 Issued
Array ( [id] => 7261268 [patent_doc_number] => 20050144216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Arithmetic circuit with multiplexed addend inputs' [patent_app_type] => utility [patent_app_number] => 11/019854 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 26498 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144216.pdf [firstpage_image] =>[orig_patent_app_number] => 11019854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019854
Arithmetic circuit with multiplexed addend inputs Dec 20, 2004 Issued
Array ( [id] => 585414 [patent_doc_number] => 07467177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Mathematical circuit with dynamic rounding' [patent_app_type] => utility [patent_app_number] => 11/019853 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 62 [patent_no_of_words] => 26501 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/467/07467177.pdf [firstpage_image] =>[orig_patent_app_number] => 11019853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019853
Mathematical circuit with dynamic rounding Dec 20, 2004 Issued
Array ( [id] => 585385 [patent_doc_number] => 07467175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-16 [patent_title] => 'Programmable logic device with pipelined DSP slices' [patent_app_type] => utility [patent_app_number] => 11/019782 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 62 [patent_no_of_words] => 26477 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/467/07467175.pdf [firstpage_image] =>[orig_patent_app_number] => 11019782 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019782
Programmable logic device with pipelined DSP slices Dec 20, 2004 Issued
Array ( [id] => 604595 [patent_doc_number] => 07433911 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Data processing apparatus and method for performing floating point addition' [patent_app_type] => utility [patent_app_number] => 11/017217 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7481 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/433/07433911.pdf [firstpage_image] =>[orig_patent_app_number] => 11017217 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/017217
Data processing apparatus and method for performing floating point addition Dec 20, 2004 Issued
Array ( [id] => 268468 [patent_doc_number] => 07567997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'Applications of cascading DSP slices' [patent_app_type] => utility [patent_app_number] => 11/019518 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 68 [patent_figures_cnt] => 73 [patent_no_of_words] => 31840 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/567/07567997.pdf [firstpage_image] =>[orig_patent_app_number] => 11019518 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019518
Applications of cascading DSP slices Dec 20, 2004 Issued
Array ( [id] => 7261241 [patent_doc_number] => 20050144212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Programmable logic device with cascading DSP slices' [patent_app_type] => utility [patent_app_number] => 11/019783 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 59 [patent_figures_cnt] => 59 [patent_no_of_words] => 26496 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144212.pdf [firstpage_image] =>[orig_patent_app_number] => 11019783 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019783
Programmable logic device with cascading DSP slices Dec 20, 2004 Issued
Array ( [id] => 5650805 [patent_doc_number] => 20060136540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-22 [patent_title] => 'Enhanced fused multiply-add operation' [patent_app_type] => utility [patent_app_number] => 11/019921 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2704 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20060136540.pdf [firstpage_image] =>[orig_patent_app_number] => 11019921 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/019921
Enhanced fused multiply-add operation Dec 20, 2004 Issued
Array ( [id] => 7006672 [patent_doc_number] => 20050171985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Data coding method and corresponding data processing unit having a coding/decoding circuit' [patent_app_type] => utility [patent_app_number] => 11/018972 [patent_app_country] => US [patent_app_date] => 2004-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5047 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20050171985.pdf [firstpage_image] =>[orig_patent_app_number] => 11018972 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018972
Data coding method and corresponding data processing unit having a coding/decoding circuit Dec 20, 2004 Issued
Array ( [id] => 6999200 [patent_doc_number] => 20050138096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-23 [patent_title] => 'Non-linear digital rank filtering of input signal values' [patent_app_type] => utility [patent_app_number] => 11/018865 [patent_app_country] => US [patent_app_date] => 2004-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10419 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20050138096.pdf [firstpage_image] =>[orig_patent_app_number] => 11018865 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/018865
Non-linear digital rank filtering of input signal values Dec 19, 2004 Issued
Array ( [id] => 57700 [patent_doc_number] => 07774397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'FFT/IFFT processor' [patent_app_type] => utility [patent_app_number] => 11/003924 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2353 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/774/07774397.pdf [firstpage_image] =>[orig_patent_app_number] => 11003924 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/003924
FFT/IFFT processor Dec 2, 2004 Issued
Array ( [id] => 135967 [patent_doc_number] => 07702712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-20 [patent_title] => 'FFT architecture and method' [patent_app_type] => utility [patent_app_number] => 11/002478 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8291 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/702/07702712.pdf [firstpage_image] =>[orig_patent_app_number] => 11002478 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/002478
FFT architecture and method Nov 30, 2004 Issued
Array ( [id] => 171728 [patent_doc_number] => 07668895 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Galois field computation' [patent_app_type] => utility [patent_app_number] => 11/000013 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3940 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/668/07668895.pdf [firstpage_image] =>[orig_patent_app_number] => 11000013 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000013
Galois field computation Nov 30, 2004 Issued
Array ( [id] => 597758 [patent_doc_number] => 07447724 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Error function calculation device and error function calculation method' [patent_app_type] => utility [patent_app_number] => 10/999293 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13647 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/447/07447724.pdf [firstpage_image] =>[orig_patent_app_number] => 10999293 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999293
Error function calculation device and error function calculation method Nov 28, 2004 Issued
Array ( [id] => 798968 [patent_doc_number] => 07428562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-23 [patent_title] => 'Self-authenticating quantum random number generator' [patent_app_type] => utility [patent_app_number] => 10/998208 [patent_app_country] => US [patent_app_date] => 2004-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6551 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/428/07428562.pdf [firstpage_image] =>[orig_patent_app_number] => 10998208 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/998208
Self-authenticating quantum random number generator Nov 25, 2004 Issued
Array ( [id] => 7184789 [patent_doc_number] => 20050125480 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Method and apparatus for multiplying based on booth\'s algorithm' [patent_app_type] => utility [patent_app_number] => 10/986095 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20050125480.pdf [firstpage_image] =>[orig_patent_app_number] => 10986095 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/986095
Method and apparatus for multiplying based on booth's algorithm Nov 11, 2004 Abandoned
Array ( [id] => 7106195 [patent_doc_number] => 20050108002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Signal analyzing method, signal synthesizing method of complex exponential modulation filter bank, program thereof and recording medium thereof' [patent_app_type] => utility [patent_app_number] => 10/986624 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13066 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20050108002.pdf [firstpage_image] =>[orig_patent_app_number] => 10986624 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/986624
Signal analyzing method, signal synthesizing method of complex exponential modulation filter bank, program thereof and recording medium thereof Nov 11, 2004 Issued
Array ( [id] => 5633332 [patent_doc_number] => 20060149803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Multipurpose functional unit with multiply-add and format conversion pipeline' [patent_app_type] => utility [patent_app_number] => 10/985674 [patent_app_country] => US [patent_app_date] => 2004-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 23932 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20060149803.pdf [firstpage_image] =>[orig_patent_app_number] => 10985674 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985674
Multipurpose functional unit with multiply-add and format conversion pipeline Nov 9, 2004 Issued
Array ( [id] => 5102683 [patent_doc_number] => 20070185945 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-09 [patent_title] => 'Reilible Recording of Input Values' [patent_app_type] => utility [patent_app_number] => 10/578426 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4959 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20070185945.pdf [firstpage_image] =>[orig_patent_app_number] => 10578426 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/578426
Reliable recording of input values Nov 7, 2004 Issued
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