Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12735220 [patent_doc_number] => 20180136907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => RANDOMNESS TEST APPARATUS AND METHOD FOR RANDOM NUMBER GENERATOR [patent_app_type] => utility [patent_app_number] => 15/404826 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11887 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15404826 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/404826
Randomness test apparatus and method for random number generator Jan 11, 2017 Issued
Array ( [id] => 12914383 [patent_doc_number] => 20180196637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => Calculating Normalized Metrics [patent_app_type] => utility [patent_app_number] => 15/404599 [patent_app_country] => US [patent_app_date] => 2017-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5845 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15404599 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/404599
Calculating normalized metrics Jan 11, 2017 Issued
Array ( [id] => 14202673 [patent_doc_number] => 10268452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Automatic control system and method for a true random number generator [patent_app_type] => utility [patent_app_number] => 15/397490 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5425 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397490 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/397490
Automatic control system and method for a true random number generator Jan 2, 2017 Issued
Array ( [id] => 12892192 [patent_doc_number] => 20180189239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => HETEROGENEOUS HARDWARE ACCELERATOR ARCHITECTURE FOR PROCESSING SPARSE MATRIX DATA WITH SKEWED NON-ZERO DISTRIBUTIONS [patent_app_type] => utility [patent_app_number] => 15/396513 [patent_app_country] => US [patent_app_date] => 2016-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396513 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396513
Heterogeneous hardware accelerator architecture for processing sparse matrix data with skewed non-zero distributions Dec 30, 2016 Issued
Array ( [id] => 12898624 [patent_doc_number] => 20180191383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => TRANSFORMATION BASED FILTER FOR INTERPOLATION OR DECIMATION [patent_app_type] => utility [patent_app_number] => 15/395135 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5269 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395135 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395135
Transformation based filter for interpolation or decimation Dec 29, 2016 Issued
Array ( [id] => 12892183 [patent_doc_number] => 20180189236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => DISTRIBUTED MATRIX MULTIPLICATION FOR NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 15/395527 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16792 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395527 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395527
Distributed matrix multiplication for neural networks Dec 29, 2016 Issued
Array ( [id] => 12892189 [patent_doc_number] => 20180189238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => MAX POOLING IN A MATRIX PROCESSING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 15/395786 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15703 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395786 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395786
Max pooling in a matrix processing architecture Dec 29, 2016 Issued
Array ( [id] => 12892186 [patent_doc_number] => 20180189237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => WINOGRAD ALGORITHM ON A MATRIX PROCESSING ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 15/395542 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395542 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395542
Winograd algorithm on a matrix processing architecture Dec 29, 2016 Issued
Array ( [id] => 13226475 [patent_doc_number] => 10127013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-13 [patent_title] => Specialized processing blocks with fixed-point and floating-point structures [patent_app_type] => utility [patent_app_number] => 15/390358 [patent_app_country] => US [patent_app_date] => 2016-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5789 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15390358 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/390358
Specialized processing blocks with fixed-point and floating-point structures Dec 22, 2016 Issued
Array ( [id] => 14555349 [patent_doc_number] => 10346136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Device and method for managing performance of quantum noise-based random number generator [patent_app_type] => utility [patent_app_number] => 15/570624 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9872 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15570624 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/570624
Device and method for managing performance of quantum noise-based random number generator Dec 18, 2016 Issued
Array ( [id] => 14034377 [patent_doc_number] => 10228939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-12 [patent_title] => Efficient conversion of numbers from database floating point format to binary integer format [patent_app_type] => utility [patent_app_number] => 15/378701 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7303 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15378701 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/378701
Efficient conversion of numbers from database floating point format to binary integer format Dec 13, 2016 Issued
Array ( [id] => 13254811 [patent_doc_number] => 10140096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-11-27 [patent_title] => Preventing ring oscillator phase-lock [patent_app_type] => utility [patent_app_number] => 15/379103 [patent_app_country] => US [patent_app_date] => 2016-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 9470 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15379103 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/379103
Preventing ring oscillator phase-lock Dec 13, 2016 Issued
Array ( [id] => 12819676 [patent_doc_number] => 20180165064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => PARTIAL SQUARE ROOT CALCULATION [patent_app_type] => utility [patent_app_number] => 15/376947 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376947 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/376947
Partial square root calculation Dec 12, 2016 Issued
Array ( [id] => 12820228 [patent_doc_number] => 20180165248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-14 [patent_title] => SYSTEMS AND METHODS FOR PERFORMING LINEAR ALGEBRA OPERATIONS USING MULTI-MODE OPTICS [patent_app_type] => utility [patent_app_number] => 15/376500 [patent_app_country] => US [patent_app_date] => 2016-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12277 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15376500 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/376500
Systems and methods for performing linear algebra operations using multi-mode optics Dec 11, 2016 Issued
Array ( [id] => 12796798 [patent_doc_number] => 20180157435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => ACCELERATION AND DYNAMIC ALLOCATION OF RANDOM DATA BANDWIDTH IN MULTI-CORE PROCESSORS [patent_app_type] => utility [patent_app_number] => 15/370440 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9150 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370440 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/370440
Acceleration and dynamic allocation of random data bandwidth in multi-core processors Dec 5, 2016 Issued
Array ( [id] => 13807105 [patent_doc_number] => 10180819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-15 [patent_title] => Processing fixed and variable length numbers [patent_app_type] => utility [patent_app_number] => 15/334349 [patent_app_country] => US [patent_app_date] => 2016-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10480 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15334349 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/334349
Processing fixed and variable length numbers Oct 25, 2016 Issued
Array ( [id] => 11440419 [patent_doc_number] => 20170041440 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'DATA COMPRESSION FOR PRIORITY BASED DATA TRAFFIC, ON AN AGGREGATE TRAFFIC LEVEL, IN A MULTI STREAM COMMUNICATIONS SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/333924 [patent_app_country] => US [patent_app_date] => 2016-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 22292 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15333924 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/333924
Data compression for priority based data traffic, on an aggregate traffic level, in a multi stream communications system Oct 24, 2016 Issued
Array ( [id] => 11423511 [patent_doc_number] => 20170031655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'Rounding Floating Point Numbers' [patent_app_type] => utility [patent_app_number] => 15/292368 [patent_app_country] => US [patent_app_date] => 2016-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15292368 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/292368
Rounding floating point numbers Oct 12, 2016 Issued
Array ( [id] => 13226479 [patent_doc_number] => 10127015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Decimal multiply and shift instruction [patent_app_type] => utility [patent_app_number] => 15/281223 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9498 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281223 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/281223
Decimal multiply and shift instruction Sep 29, 2016 Issued
Array ( [id] => 13767209 [patent_doc_number] => 10175946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Perform sign operation decimal instruction [patent_app_type] => utility [patent_app_number] => 15/281173 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 10253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15281173 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/281173
Perform sign operation decimal instruction Sep 29, 2016 Issued
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