Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 552521 [patent_doc_number] => 07174356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Complex multiplication method and apparatus with phase rotation' [patent_app_type] => utility [patent_app_number] => 10/602951 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4507 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/174/07174356.pdf [firstpage_image] =>[orig_patent_app_number] => 10602951 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/602951
Complex multiplication method and apparatus with phase rotation Jun 23, 2003 Issued
Array ( [id] => 27053 [patent_doc_number] => 07801936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Method of generating complex waveforms and modulating signals' [patent_app_type] => utility [patent_app_number] => 10/463482 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 10413 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/801/07801936.pdf [firstpage_image] =>[orig_patent_app_number] => 10463482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463482
Method of generating complex waveforms and modulating signals Jun 16, 2003 Issued
Array ( [id] => 171730 [patent_doc_number] => 07668897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'Result partitioning within SIMD data processing systems' [patent_app_type] => utility [patent_app_number] => 10/461880 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3261 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/668/07668897.pdf [firstpage_image] =>[orig_patent_app_number] => 10461880 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/461880
Result partitioning within SIMD data processing systems Jun 15, 2003 Issued
Array ( [id] => 633117 [patent_doc_number] => 07133886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-07 [patent_title] => 'Interactive adaptive filter and interactive adaptive filtering method thereof' [patent_app_type] => utility [patent_app_number] => 10/455932 [patent_app_country] => US [patent_app_date] => 2003-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4726 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/133/07133886.pdf [firstpage_image] =>[orig_patent_app_number] => 10455932 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/455932
Interactive adaptive filter and interactive adaptive filtering method thereof Jun 5, 2003 Issued
Array ( [id] => 7357666 [patent_doc_number] => 20040249873 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Ultra fast comparator and method therefor' [patent_app_type] => new [patent_app_number] => 10/454540 [patent_app_country] => US [patent_app_date] => 2003-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7670 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20040249873.pdf [firstpage_image] =>[orig_patent_app_number] => 10454540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/454540
Ultra fast comparator and method therefor Jun 4, 2003 Abandoned
Array ( [id] => 7352031 [patent_doc_number] => 20040193665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Bi-quad digital filter configured with a bit binary rate multiplier' [patent_app_type] => new [patent_app_number] => 10/453901 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5281 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193665.pdf [firstpage_image] =>[orig_patent_app_number] => 10453901 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453901
Bi-quad digital filter configured with a bit binary rate multiplier Jun 1, 2003 Issued
Array ( [id] => 648901 [patent_doc_number] => 07120661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-10 [patent_title] => 'Bit exactness support in dual-MAC architecture' [patent_app_type] => utility [patent_app_number] => 10/447352 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2875 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/120/07120661.pdf [firstpage_image] =>[orig_patent_app_number] => 10447352 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/447352
Bit exactness support in dual-MAC architecture May 28, 2003 Issued
Array ( [id] => 400385 [patent_doc_number] => 07296047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-13 [patent_title] => 'Method and apparatus for solving overdetermined systems of interval linear equations' [patent_app_type] => utility [patent_app_number] => 10/447371 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4943 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/296/07296047.pdf [firstpage_image] =>[orig_patent_app_number] => 10447371 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/447371
Method and apparatus for solving overdetermined systems of interval linear equations May 27, 2003 Issued
Array ( [id] => 904579 [patent_doc_number] => 07340498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Apparatus and method for determining fixed point in mobile communication system' [patent_app_type] => utility [patent_app_number] => 10/446108 [patent_app_country] => US [patent_app_date] => 2003-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3305 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/340/07340498.pdf [firstpage_image] =>[orig_patent_app_number] => 10446108 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/446108
Apparatus and method for determining fixed point in mobile communication system May 27, 2003 Issued
Array ( [id] => 546859 [patent_doc_number] => 07185039 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-27 [patent_title] => 'Multiplier for modular exponentiation' [patent_app_type] => utility [patent_app_number] => 10/441651 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6752 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/185/07185039.pdf [firstpage_image] =>[orig_patent_app_number] => 10441651 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441651
Multiplier for modular exponentiation May 18, 2003 Issued
Array ( [id] => 434736 [patent_doc_number] => 07266577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Modular multiplication apparatus, modular multiplication method, and modular exponentiation apparatus' [patent_app_type] => utility [patent_app_number] => 10/440362 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 18550 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/266/07266577.pdf [firstpage_image] =>[orig_patent_app_number] => 10440362 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/440362
Modular multiplication apparatus, modular multiplication method, and modular exponentiation apparatus May 18, 2003 Issued
Array ( [id] => 7057231 [patent_doc_number] => 20050278406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'System and computer-implemented method for evaluating integrals using stratification by rank-1 lattices' [patent_app_type] => utility [patent_app_number] => 10/439311 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 10581 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0278/20050278406.pdf [firstpage_image] =>[orig_patent_app_number] => 10439311 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439311
System and computer-implemented method for evaluating integrals using stratification by rank-1 lattices May 14, 2003 Abandoned
Array ( [id] => 6771144 [patent_doc_number] => 20030217084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Method of generating a cycle-efficient bit-reverse index array for a wireless communication system' [patent_app_type] => new [patent_app_number] => 10/438241 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2201 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0217/20030217084.pdf [firstpage_image] =>[orig_patent_app_number] => 10438241 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438241
Method of generating a cycle-efficient bit-reverse index array for a wireless communication system May 13, 2003 Issued
Array ( [id] => 511849 [patent_doc_number] => 07206801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-17 [patent_title] => 'Digital multiplier with reduced spurious switching by means of Latch Adders' [patent_app_type] => utility [patent_app_number] => 10/437502 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5218 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/206/07206801.pdf [firstpage_image] =>[orig_patent_app_number] => 10437502 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/437502
Digital multiplier with reduced spurious switching by means of Latch Adders May 13, 2003 Issued
Array ( [id] => 626155 [patent_doc_number] => 07139786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Method and apparatus for efficiently performing a square root operation' [patent_app_type] => utility [patent_app_number] => 10/436610 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4666 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139786.pdf [firstpage_image] =>[orig_patent_app_number] => 10436610 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436610
Method and apparatus for efficiently performing a square root operation May 11, 2003 Issued
Array ( [id] => 7434989 [patent_doc_number] => 20040230633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Decimal multiplication for superscaler processors' [patent_app_type] => new [patent_app_number] => 10/436392 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5767 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20040230633.pdf [firstpage_image] =>[orig_patent_app_number] => 10436392 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436392
Decimal multiplication for superscaler processors May 11, 2003 Issued
Array ( [id] => 615522 [patent_doc_number] => 07149767 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'Method and system for determining quotient digits for decimal division in a superscaler processor' [patent_app_type] => utility [patent_app_number] => 10/436322 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6776 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149767.pdf [firstpage_image] =>[orig_patent_app_number] => 10436322 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436322
Method and system for determining quotient digits for decimal division in a superscaler processor May 11, 2003 Issued
Array ( [id] => 7605817 [patent_doc_number] => 07099905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Novelty calculator system for amusement' [patent_app_type] => utility [patent_app_number] => 10/435240 [patent_app_country] => US [patent_app_date] => 2003-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3219 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/099/07099905.pdf [firstpage_image] =>[orig_patent_app_number] => 10435240 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/435240
Novelty calculator system for amusement May 9, 2003 Issued
Array ( [id] => 336443 [patent_doc_number] => 07509366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Multiplier array processing system with enhanced utilization at lower precision' [patent_app_type] => utility [patent_app_number] => 10/418113 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5545 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509366.pdf [firstpage_image] =>[orig_patent_app_number] => 10418113 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/418113
Multiplier array processing system with enhanced utilization at lower precision Apr 17, 2003 Issued
Array ( [id] => 7476714 [patent_doc_number] => 20040098441 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'System, method, and apparatus for division coupled with truncation of signed binary numbers' [patent_app_type] => new [patent_app_number] => 10/414580 [patent_app_country] => US [patent_app_date] => 2003-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2115 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20040098441.pdf [firstpage_image] =>[orig_patent_app_number] => 10414580 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/414580
System, method, and apparatus for division coupled with truncation of signed binary numbers Apr 14, 2003 Issued
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