
Richard L Schilling
Examiner (ID: 9999)
Most Active Art Unit | 1506 |
Art Unit(s) | 1795, 1715, 1302, 1113, 1506, 1752 |
Total Applications | 3259 |
Issued Applications | 2786 |
Pending Applications | 23 |
Abandoned Applications | 403 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 5671370
[patent_doc_number] => 20060176724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-10
[patent_title] => 'Phase change memory device'
[patent_app_type] => utility
[patent_app_number] => 11/349959
[patent_app_country] => US
[patent_app_date] => 2006-02-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 22
[patent_no_of_words] => 5674
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0176/20060176724.pdf
[firstpage_image] =>[orig_patent_app_number] => 11349959
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/349959 | Phase change memory device | Feb 8, 2006 | Issued |
Array
(
[id] => 5099941
[patent_doc_number] => 20070183202
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-09
[patent_title] => 'Memory array segmentation and methods'
[patent_app_type] => utility
[patent_app_number] => 11/349854
[patent_app_country] => US
[patent_app_date] => 2006-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4994
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 27
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20070183202.pdf
[firstpage_image] =>[orig_patent_app_number] => 11349854
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/349854 | Memory array segmentation and methods | Feb 7, 2006 | Issued |
Array
(
[id] => 5099926
[patent_doc_number] => 20070183187
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-08-09
[patent_title] => 'Synthetic anti-ferromagnetic structure with non-magnetic spacer for MRAM applications'
[patent_app_type] => utility
[patent_app_number] => 11/350119
[patent_app_country] => US
[patent_app_date] => 2006-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 7095
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0183/20070183187.pdf
[firstpage_image] =>[orig_patent_app_number] => 11350119
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/350119 | Synthetic anti-ferromagnetic structure with non-magnetic spacer for MRAM applications | Feb 7, 2006 | Issued |
Array
(
[id] => 5147267
[patent_doc_number] => 20070047321
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-03-01
[patent_title] => 'Memory system with two voltage sources'
[patent_app_type] => utility
[patent_app_number] => 11/349106
[patent_app_country] => US
[patent_app_date] => 2006-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 995
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0047/20070047321.pdf
[firstpage_image] =>[orig_patent_app_number] => 11349106
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/349106 | Memory system with two voltage sources | Feb 7, 2006 | Abandoned |
Array
(
[id] => 5676585
[patent_doc_number] => 20060181940
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-08-17
[patent_title] => 'Memory address generating circuit and memory controller using the same'
[patent_app_type] => utility
[patent_app_number] => 11/349860
[patent_app_country] => US
[patent_app_date] => 2006-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2797
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0181/20060181940.pdf
[firstpage_image] =>[orig_patent_app_number] => 11349860
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/349860 | Memory address generating circuit and memory controller using the same | Feb 7, 2006 | Issued |
Array
(
[id] => 879257
[patent_doc_number] => 07359261
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-04-15
[patent_title] => 'Memory repair system and method'
[patent_app_type] => utility
[patent_app_number] => 11/349460
[patent_app_country] => US
[patent_app_date] => 2006-02-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 9049
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/359/07359261.pdf
[firstpage_image] =>[orig_patent_app_number] => 11349460
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/349460 | Memory repair system and method | Feb 6, 2006 | Issued |
Array
(
[id] => 5871390
[patent_doc_number] => 20060164897
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-27
[patent_title] => 'Semiconductor storage device having page copying function'
[patent_app_type] => utility
[patent_app_number] => 11/328681
[patent_app_country] => US
[patent_app_date] => 2006-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4760
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0164/20060164897.pdf
[firstpage_image] =>[orig_patent_app_number] => 11328681
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/328681 | Semiconductor storage device having page copying function | Jan 8, 2006 | Issued |
Array
(
[id] => 346123
[patent_doc_number] => 07499315
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-03
[patent_title] => 'Programmable matrix array with chalcogenide material'
[patent_app_type] => utility
[patent_app_number] => 11/318789
[patent_app_country] => US
[patent_app_date] => 2005-12-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 90
[patent_no_of_words] => 39211
[patent_no_of_claims] => 108
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/499/07499315.pdf
[firstpage_image] =>[orig_patent_app_number] => 11318789
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/318789 | Programmable matrix array with chalcogenide material | Dec 23, 2005 | Issued |
Array
(
[id] => 5647418
[patent_doc_number] => 20060133150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-06-22
[patent_title] => 'Semiconductor memory device capable of setting a negative threshold voltage'
[patent_app_type] => utility
[patent_app_number] => 11/300364
[patent_app_country] => US
[patent_app_date] => 2005-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 10288
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20060133150.pdf
[firstpage_image] =>[orig_patent_app_number] => 11300364
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/300364 | Semiconductor memory device capable of setting a negative threshold voltage | Dec 14, 2005 | Issued |
Array
(
[id] => 5251854
[patent_doc_number] => 20070133310
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-14
[patent_title] => 'Memory using a single-node data, address and control bus'
[patent_app_type] => utility
[patent_app_number] => 11/301670
[patent_app_country] => US
[patent_app_date] => 2005-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3196
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20070133310.pdf
[firstpage_image] =>[orig_patent_app_number] => 11301670
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/301670 | Memory using a single-node data, address and control bus | Dec 12, 2005 | Issued |
Array
(
[id] => 399214
[patent_doc_number] => 07295462
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-13
[patent_title] => 'Method and apparatus processing variable resistance memory cell write operation'
[patent_app_type] => utility
[patent_app_number] => 11/298614
[patent_app_country] => US
[patent_app_date] => 2005-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4548
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/295/07295462.pdf
[firstpage_image] =>[orig_patent_app_number] => 11298614
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/298614 | Method and apparatus processing variable resistance memory cell write operation | Dec 11, 2005 | Issued |
Array
(
[id] => 459706
[patent_doc_number] => 07245555
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-07-17
[patent_title] => 'Automatic address transition detection (ATD) control for reduction of sense amplifier power consumption'
[patent_app_type] => utility
[patent_app_number] => 11/301040
[patent_app_country] => US
[patent_app_date] => 2005-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 5049
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/245/07245555.pdf
[firstpage_image] =>[orig_patent_app_number] => 11301040
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/301040 | Automatic address transition detection (ATD) control for reduction of sense amplifier power consumption | Dec 11, 2005 | Issued |
Array
(
[id] => 5692842
[patent_doc_number] => 20060152988
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-07-13
[patent_title] => 'Memory component having a novel arrangement of the bit lines'
[patent_app_type] => utility
[patent_app_number] => 11/301354
[patent_app_country] => US
[patent_app_date] => 2005-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3393
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0152/20060152988.pdf
[firstpage_image] =>[orig_patent_app_number] => 11301354
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/301354 | Memory component having a novel arrangement of the bit lines | Dec 11, 2005 | Issued |
Array
(
[id] => 360657
[patent_doc_number] => 07486536
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-02-03
[patent_title] => 'Phase-changeable memory device and method of programming the same'
[patent_app_type] => utility
[patent_app_number] => 11/301322
[patent_app_country] => US
[patent_app_date] => 2005-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5561
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/486/07486536.pdf
[firstpage_image] =>[orig_patent_app_number] => 11301322
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/301322 | Phase-changeable memory device and method of programming the same | Dec 11, 2005 | Issued |
Array
(
[id] => 430018
[patent_doc_number] => 07269062
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-11
[patent_title] => 'Gated diode nonvolatile memory cell'
[patent_app_type] => utility
[patent_app_number] => 11/298288
[patent_app_country] => US
[patent_app_date] => 2005-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 52
[patent_no_of_words] => 8288
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/269/07269062.pdf
[firstpage_image] =>[orig_patent_app_number] => 11298288
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/298288 | Gated diode nonvolatile memory cell | Dec 8, 2005 | Issued |
Array
(
[id] => 5251836
[patent_doc_number] => 20070133292
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-06-14
[patent_title] => 'Method for operating gated diode nonvolatile memory cell'
[patent_app_type] => utility
[patent_app_number] => 11/299310
[patent_app_country] => US
[patent_app_date] => 2005-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 8264
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0133/20070133292.pdf
[firstpage_image] =>[orig_patent_app_number] => 11299310
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/299310 | Method for operating gated diode nonvolatile memory cell | Dec 8, 2005 | Issued |
Array
(
[id] => 413300
[patent_doc_number] => 07283389
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-16
[patent_title] => 'Gated diode nonvolatile memory cell array'
[patent_app_type] => utility
[patent_app_number] => 11/298912
[patent_app_country] => US
[patent_app_date] => 2005-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 52
[patent_no_of_words] => 8302
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/283/07283389.pdf
[firstpage_image] =>[orig_patent_app_number] => 11298912
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/298912 | Gated diode nonvolatile memory cell array | Dec 8, 2005 | Issued |
Array
(
[id] => 517909
[patent_doc_number] => 07196952
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-03-27
[patent_title] => 'Column/sector redundancy CAM fast programming scheme using regular memory core array in multi-plane flash memory device'
[patent_app_type] => utility
[patent_app_number] => 11/295878
[patent_app_country] => US
[patent_app_date] => 2005-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2938
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 155
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/196/07196952.pdf
[firstpage_image] =>[orig_patent_app_number] => 11295878
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/295878 | Column/sector redundancy CAM fast programming scheme using regular memory core array in multi-plane flash memory device | Dec 6, 2005 | Issued |
Array
(
[id] => 315869
[patent_doc_number] => 07525847
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-04-28
[patent_title] => 'Semiconductor device and methods of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/282806
[patent_app_country] => US
[patent_app_date] => 2005-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 6966
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/525/07525847.pdf
[firstpage_image] =>[orig_patent_app_number] => 11282806
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/282806 | Semiconductor device and methods of manufacturing the same | Nov 17, 2005 | Issued |
Array
(
[id] => 5636166
[patent_doc_number] => 20060067139
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'Memory'
[patent_app_type] => utility
[patent_app_number] => 11/281492
[patent_app_country] => US
[patent_app_date] => 2005-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
[patent_figures_cnt] => 43
[patent_no_of_words] => 23201
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0067/20060067139.pdf
[firstpage_image] =>[orig_patent_app_number] => 11281492
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/281492 | Memory | Nov 17, 2005 | Abandoned |