Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 712983 [patent_doc_number] => 07062525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-13 [patent_title] => 'Circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method' [patent_app_type] => utility [patent_app_number] => 10/232001 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 7188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/062/07062525.pdf [firstpage_image] =>[orig_patent_app_number] => 10232001 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232001
Circuit and method for normalizing and rounding floating-point results and processor incorporating the circuit or the method Aug 29, 2002 Issued
Array ( [id] => 6665218 [patent_doc_number] => 20030204545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Method for implementing a multiplier-less FIR filter' [patent_app_type] => new [patent_app_number] => 10/230142 [patent_app_country] => US [patent_app_date] => 2002-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2615 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20030204545.pdf [firstpage_image] =>[orig_patent_app_number] => 10230142 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/230142
Method for implementing a multiplier-less FIR filter Aug 28, 2002 Issued
Array ( [id] => 744529 [patent_doc_number] => 07035891 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Reduced-hardware soft error detection' [patent_app_type] => utility [patent_app_number] => 10/228432 [patent_app_country] => US [patent_app_date] => 2002-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5232 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035891.pdf [firstpage_image] =>[orig_patent_app_number] => 10228432 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/228432
Reduced-hardware soft error detection Aug 26, 2002 Issued
Array ( [id] => 730474 [patent_doc_number] => 07047262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Entropy estimation and decimation for improving the randomness of true random number generation' [patent_app_type] => utility [patent_app_number] => 10/224992 [patent_app_country] => US [patent_app_date] => 2002-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2014 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/047/07047262.pdf [firstpage_image] =>[orig_patent_app_number] => 10224992 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/224992
Entropy estimation and decimation for improving the randomness of true random number generation Aug 20, 2002 Issued
Array ( [id] => 1288599 [patent_doc_number] => 06647403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'Method and digital signal processing equipment for performing digital signal processing calculation' [patent_app_type] => B2 [patent_app_number] => 10/219823 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3053 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647403.pdf [firstpage_image] =>[orig_patent_app_number] => 10219823 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/219823
Method and digital signal processing equipment for performing digital signal processing calculation Aug 15, 2002 Issued
Array ( [id] => 6839746 [patent_doc_number] => 20030037086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Method and apparatus for facilitating exception-free arithmetic in a computer system' [patent_app_type] => new [patent_app_number] => 10/222612 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6109 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037086.pdf [firstpage_image] =>[orig_patent_app_number] => 10222612 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/222612
Method and apparatus for facilitating exception-free arithmetic in a computer system Aug 15, 2002 Issued
Array ( [id] => 7315930 [patent_doc_number] => 20040034674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Generator circuit for generating large numbers' [patent_app_type] => new [patent_app_number] => 10/219741 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2358 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20040034674.pdf [firstpage_image] =>[orig_patent_app_number] => 10219741 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/219741
Generator circuit for generating large numbers Aug 15, 2002 Issued
Array ( [id] => 777645 [patent_doc_number] => 07003536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Reduced complexity fast hadamard transform' [patent_app_type] => utility [patent_app_number] => 10/219962 [patent_app_country] => US [patent_app_date] => 2002-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 10692 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003536.pdf [firstpage_image] =>[orig_patent_app_number] => 10219962 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/219962
Reduced complexity fast hadamard transform Aug 14, 2002 Issued
Array ( [id] => 6717227 [patent_doc_number] => 20030028575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'A Microprocessor and a digital signal processor including adder and multiplier circuits employing logic gates having discrete and weighted inputs' [patent_app_type] => new [patent_app_number] => 10/219714 [patent_app_country] => US [patent_app_date] => 2002-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6656 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028575.pdf [firstpage_image] =>[orig_patent_app_number] => 10219714 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/219714
A Microprocessor and a digital signal processor including adder and multiplier circuits employing logic gates having discrete and weighted inputs Aug 14, 2002 Abandoned
Array ( [id] => 748959 [patent_doc_number] => 07031994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Matrix transposition in a computer system' [patent_app_type] => utility [patent_app_number] => 10/218312 [patent_app_country] => US [patent_app_date] => 2002-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9419 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/031/07031994.pdf [firstpage_image] =>[orig_patent_app_number] => 10218312 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/218312
Matrix transposition in a computer system Aug 12, 2002 Issued
Array ( [id] => 7393056 [patent_doc_number] => 20040030735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Clock balanced segmentation digital filter provided with optimun area of data path' [patent_app_type] => new [patent_app_number] => 10/215011 [patent_app_country] => US [patent_app_date] => 2002-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1764 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20040030735.pdf [firstpage_image] =>[orig_patent_app_number] => 10215011 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/215011
Clock balanced segmentation digital filter provided with optimun area of data path Aug 8, 2002 Issued
Array ( [id] => 777662 [patent_doc_number] => 07003541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-02-21 [patent_title] => 'Zero-knowledge proving system and method' [patent_app_type] => utility [patent_app_number] => 10/212172 [patent_app_country] => US [patent_app_date] => 2002-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 12216 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/003/07003541.pdf [firstpage_image] =>[orig_patent_app_number] => 10212172 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212172
Zero-knowledge proving system and method Aug 5, 2002 Issued
Array ( [id] => 6655689 [patent_doc_number] => 20030009504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith' [patent_app_type] => new [patent_app_number] => 10/211866 [patent_app_country] => US [patent_app_date] => 2002-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6662 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20030009504.pdf [firstpage_image] =>[orig_patent_app_number] => 10211866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/211866
Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith Aug 1, 2002 Abandoned
Array ( [id] => 7406519 [patent_doc_number] => 20040019617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Latching electronic circuit for random number generation' [patent_app_type] => new [patent_app_number] => 10/205231 [patent_app_country] => US [patent_app_date] => 2002-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2421 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20040019617.pdf [firstpage_image] =>[orig_patent_app_number] => 10205231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/205231
Latching electronic circuit for random number generation Jul 24, 2002 Issued
Array ( [id] => 1020789 [patent_doc_number] => 06892215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Fast parallel cascaded array modular multiplier' [patent_app_type] => utility [patent_app_number] => 10/192911 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2409 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1446 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/892/06892215.pdf [firstpage_image] =>[orig_patent_app_number] => 10192911 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192911
Fast parallel cascaded array modular multiplier Jul 9, 2002 Issued
Array ( [id] => 1007629 [patent_doc_number] => 06907440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Systolic cylindrical array modular multiplier' [patent_app_type] => utility [patent_app_number] => 10/193441 [patent_app_country] => US [patent_app_date] => 2002-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2441 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 2396 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/907/06907440.pdf [firstpage_image] =>[orig_patent_app_number] => 10193441 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/193441
Systolic cylindrical array modular multiplier Jul 9, 2002 Issued
Array ( [id] => 933131 [patent_doc_number] => 06981009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-27 [patent_title] => 'Apparatus and method for computing a logarithm of a floating-point number' [patent_app_type] => utility [patent_app_number] => 10/191214 [patent_app_country] => US [patent_app_date] => 2002-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4063 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981009.pdf [firstpage_image] =>[orig_patent_app_number] => 10191214 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/191214
Apparatus and method for computing a logarithm of a floating-point number Jul 8, 2002 Issued
Array ( [id] => 485110 [patent_doc_number] => 07225216 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-29 [patent_title] => 'Method and system for a floating point multiply-accumulator' [patent_app_type] => utility [patent_app_number] => 10/192391 [patent_app_country] => US [patent_app_date] => 2002-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1250 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/225/07225216.pdf [firstpage_image] =>[orig_patent_app_number] => 10192391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/192391
Method and system for a floating point multiply-accumulator Jul 8, 2002 Issued
Array ( [id] => 773894 [patent_doc_number] => 07007058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-02-28 [patent_title] => 'Methods and apparatus for binary division using look-up table' [patent_app_type] => utility [patent_app_number] => 10/190892 [patent_app_country] => US [patent_app_date] => 2002-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6158 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/007/07007058.pdf [firstpage_image] =>[orig_patent_app_number] => 10190892 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190892
Methods and apparatus for binary division using look-up table Jul 7, 2002 Issued
Array ( [id] => 6707492 [patent_doc_number] => 20030154226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-14 [patent_title] => 'Method and system for processing complex numbers' [patent_app_type] => new [patent_app_number] => 10/189195 [patent_app_country] => US [patent_app_date] => 2002-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 16363 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20030154226.pdf [firstpage_image] =>[orig_patent_app_number] => 10189195 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/189195
Method and system for processing complex numbers Jul 4, 2002 Abandoned
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