Richard L Schilling

Array ( [id] => 5203661 [patent_doc_number] => 20070025140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-01 [patent_title] => 'SRAM cell with independent static noise margin, trip voltage, and read current optimization' [patent_app_type] => utility [patent_app_number] => 11/191348 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20070025140.pdf [firstpage_image] =>[orig_patent_app_number] => 11191348 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5641533 [patent_doc_number] => 20060279988 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'System and method for matching resistance in a non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/193924 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4751 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20060279988.pdf [firstpage_image] =>[orig_patent_app_number] => 11193924 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 413357 [patent_doc_number] => 07283418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Memory device and method having multiple address, data and command buses' [patent_app_type] => utility [patent_app_number] => 11/190270 [patent_app_country] => US [patent_app_date] => 2005-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3256 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/283/07283418.pdf [firstpage_image] =>[orig_patent_app_number] => 11190270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 387535 [patent_doc_number] => 07304906 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Method of controlling mode register set operation in memory device and circuit thereof' [patent_app_type] => utility [patent_app_number] => 11/190222 [patent_app_country] => US [patent_app_date] => 2005-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3312 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304906.pdf [firstpage_image] =>[orig_patent_app_number] => 11190222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 433585 [patent_doc_number] => 07266009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-04 [patent_title] => 'Ferroelectric memory' [patent_app_type] => utility [patent_app_number] => 11/188104 [patent_app_country] => US [patent_app_date] => 2005-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12033 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/266/07266009.pdf [firstpage_image] =>[orig_patent_app_number] => 11188104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7602625 [patent_doc_number] => 07236411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-06-26 [patent_title] => 'Programmable memory access parameters' [patent_app_type] => utility [patent_app_number] => 11/187356 [patent_app_country] => US [patent_app_date] => 2005-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3727 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/236/07236411.pdf [firstpage_image] =>[orig_patent_app_number] => 11187356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 399254 [patent_doc_number] => 07295482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Semiconductor memory device for a low voltage operation' [patent_app_type] => utility [patent_app_number] => 11/185738 [patent_app_country] => US [patent_app_date] => 2005-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12631 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/295/07295482.pdf [firstpage_image] =>[orig_patent_app_number] => 11185738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5240970 [patent_doc_number] => 20070019461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Methods and apparatus for accessing memory' [patent_app_type] => utility [patent_app_number] => 11/186606 [patent_app_country] => US [patent_app_date] => 2005-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10534 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20070019461.pdf [firstpage_image] =>[orig_patent_app_number] => 11186606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5819244 [patent_doc_number] => 20060023557 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Multiport memory' [patent_app_type] => utility [patent_app_number] => 11/184926 [patent_app_country] => US [patent_app_date] => 2005-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6539 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20060023557.pdf [firstpage_image] =>[orig_patent_app_number] => 11184926 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7220447 [patent_doc_number] => 20050254298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Channel erase type nonvolatile semiconductor memory device and electronic card and electronic apparatus using the device' [patent_app_type] => utility [patent_app_number] => 11/185228 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9821 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20050254298.pdf [firstpage_image] =>[orig_patent_app_number] => 11185228 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5239766 [patent_doc_number] => 20070018257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Electronic circuit having variable biasing' [patent_app_type] => utility [patent_app_number] => 11/184698 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6533 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20070018257.pdf [firstpage_image] =>[orig_patent_app_number] => 11184698 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 482252 [patent_doc_number] => 07224594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Glitch protect valid cell and method for maintaining a desired state value' [patent_app_type] => utility [patent_app_number] => 11/184346 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224594.pdf [firstpage_image] =>[orig_patent_app_number] => 11184346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 387504 [patent_doc_number] => 07304875 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-04 [patent_title] => 'Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same' [patent_app_type] => utility [patent_app_number] => 11/184414 [patent_app_country] => US [patent_app_date] => 2005-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9015 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/304/07304875.pdf [firstpage_image] =>[orig_patent_app_number] => 11184414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 542857 [patent_doc_number] => 07180784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Page buffer and verify method of flash memory device using the same' [patent_app_type] => utility [patent_app_number] => 11/182152 [patent_app_country] => US [patent_app_date] => 2005-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3027 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180784.pdf [firstpage_image] =>[orig_patent_app_number] => 11182152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 525781 [patent_doc_number] => 07193876 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-20 [patent_title] => 'Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors' [patent_app_type] => utility [patent_app_number] => 11/181534 [patent_app_country] => US [patent_app_date] => 2005-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9382 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193876.pdf [firstpage_image] =>[orig_patent_app_number] => 11181534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5893628 [patent_doc_number] => 20060002166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Semiconductor memory device, electronic card and electronic device' [patent_app_type] => utility [patent_app_number] => 11/172252 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4936 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20060002166.pdf [firstpage_image] =>[orig_patent_app_number] => 11172252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5600927 [patent_doc_number] => 20060291272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Static random access memory cell using chalcogenide' [patent_app_type] => utility [patent_app_number] => 11/158619 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7212 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20060291272.pdf [firstpage_image] =>[orig_patent_app_number] => 11158619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6950975 [patent_doc_number] => 20050226069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-13 [patent_title] => 'Semiconductor device using high-speed sense amplifier' [patent_app_type] => utility [patent_app_number] => 11/146119 [patent_app_country] => US [patent_app_date] => 2005-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8963 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20050226069.pdf [firstpage_image] =>[orig_patent_app_number] => 11146119 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 902529 [patent_doc_number] => 07339818 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-04 [patent_title] => 'Spintronic devices with integrated transistors' [patent_app_type] => utility [patent_app_number] => 11/146997 [patent_app_country] => US [patent_app_date] => 2005-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 7433 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/339/07339818.pdf [firstpage_image] =>[orig_patent_app_number] => 11146997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 499123 [patent_doc_number] => 07212459 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Unified multilevel cell memory' [patent_app_type] => utility [patent_app_number] => 11/126495 [patent_app_country] => US [patent_app_date] => 2005-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9867 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212459.pdf [firstpage_image] =>[orig_patent_app_number] => 11126495 [rel_patent_id] =>[rel_patent_doc_number] =>)