Richard L Schilling
Examiner (ID: 9849)
Most Active Art Unit | 1506 |
Art Unit(s) | 1506, 1752, 1302, 1795, 1715, 1113 |
Total Applications | 3259 |
Issued Applications | 2786 |
Pending Applications | 25 |
Abandoned Applications | 448 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
10/111571 | Method for multiplying divisor classes with a scalar | Apr 25, 2002 | Abandoned |
Array
(
[id] => 995738
[patent_doc_number] => 06917955
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-07-12
[patent_title] => 'FFT processor suited for a DMT engine for multichannel CO ADSL application'
[patent_app_type] => utility
[patent_app_number] => 10/132011
[patent_app_country] => US
[patent_app_date] => 2002-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 26
[patent_no_of_words] => 15903
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/917/06917955.pdf
[firstpage_image] =>[orig_patent_app_number] => 10132011
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/132011 | FFT processor suited for a DMT engine for multichannel CO ADSL application | Apr 24, 2002 | Issued |
Array
(
[id] => 6810303
[patent_doc_number] => 20030200242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-23
[patent_title] => 'Implantable medical device fast median filter'
[patent_app_type] => new
[patent_app_number] => 10/128021
[patent_app_country] => US
[patent_app_date] => 2002-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7952
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0200/20030200242.pdf
[firstpage_image] =>[orig_patent_app_number] => 10128021
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/128021 | Implantable medical device fast median filter | Apr 22, 2002 | Issued |
Array
(
[id] => 771050
[patent_doc_number] => 07010558
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-07
[patent_title] => 'Data processor with enhanced instruction execution and method'
[patent_app_type] => utility
[patent_app_number] => 10/125816
[patent_app_country] => US
[patent_app_date] => 2002-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7049
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/010/07010558.pdf
[firstpage_image] =>[orig_patent_app_number] => 10125816
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/125816 | Data processor with enhanced instruction execution and method | Apr 17, 2002 | Issued |
Array
(
[id] => 1225111
[patent_doc_number] => 06704760
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-09
[patent_title] => 'Optimized discrete fourier transform method and apparatus using prime factor algorithm'
[patent_app_type] => B2
[patent_app_number] => 10/120971
[patent_app_country] => US
[patent_app_date] => 2002-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 4477
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 235
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/704/06704760.pdf
[firstpage_image] =>[orig_patent_app_number] => 10120971
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/120971 | Optimized discrete fourier transform method and apparatus using prime factor algorithm | Apr 10, 2002 | Issued |
Array
(
[id] => 7621211
[patent_doc_number] => 06978290
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-12-20
[patent_title] => 'Carry ripple adder'
[patent_app_type] => utility
[patent_app_number] => 10/116851
[patent_app_country] => US
[patent_app_date] => 2002-04-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 5572
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/978/06978290.pdf
[firstpage_image] =>[orig_patent_app_number] => 10116851
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/116851 | Carry ripple adder | Apr 4, 2002 | Issued |
Array
(
[id] => 6731712
[patent_doc_number] => 20030187902
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Associative processor addition and subtraction'
[patent_app_type] => new
[patent_app_number] => 10/108451
[patent_app_country] => US
[patent_app_date] => 2002-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10724
[patent_no_of_claims] => 35
[patent_no_of_ind_claims] => 13
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0187/20030187902.pdf
[firstpage_image] =>[orig_patent_app_number] => 10108451
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/108451 | Associative processor addition and subtraction | Mar 28, 2002 | Issued |
Array
(
[id] => 444054
[patent_doc_number] => 07260592
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-21
[patent_title] => 'Addressing mode and/or instruction for providing sine and cosine value pairs'
[patent_app_type] => utility
[patent_app_number] => 10/107262
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4346
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/260/07260592.pdf
[firstpage_image] =>[orig_patent_app_number] => 10107262
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/107262 | Addressing mode and/or instruction for providing sine and cosine value pairs | Mar 27, 2002 | Issued |
Array
(
[id] => 937253
[patent_doc_number] => 06976047
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-13
[patent_title] => 'Skipped carry incrementer for FFT address generation'
[patent_app_type] => utility
[patent_app_number] => 10/108401
[patent_app_country] => US
[patent_app_date] => 2002-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3044
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/976/06976047.pdf
[firstpage_image] =>[orig_patent_app_number] => 10108401
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/108401 | Skipped carry incrementer for FFT address generation | Mar 27, 2002 | Issued |
Array
(
[id] => 7621212
[patent_doc_number] => 06978289
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-12-20
[patent_title] => 'Apparatus and method for minimizing accumulated rounding errors in coefficient values in a lookup table for interpolating polynomials'
[patent_app_type] => utility
[patent_app_number] => 10/108251
[patent_app_country] => US
[patent_app_date] => 2002-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 5360
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/978/06978289.pdf
[firstpage_image] =>[orig_patent_app_number] => 10108251
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/108251 | Apparatus and method for minimizing accumulated rounding errors in coefficient values in a lookup table for interpolating polynomials | Mar 25, 2002 | Issued |
Array
(
[id] => 7473791
[patent_doc_number] => 20040103135
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-27
[patent_title] => 'Multiplication logic circuit'
[patent_app_type] => new
[patent_app_number] => 10/472658
[patent_app_country] => US
[patent_app_date] => 2003-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3503
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0103/20040103135.pdf
[firstpage_image] =>[orig_patent_app_number] => 10472658
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/472658 | Multiplication logic circuit | Mar 20, 2002 | Issued |
Array
(
[id] => 6752151
[patent_doc_number] => 20030046672
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-03-06
[patent_title] => 'Development system of microprocessor for application program including integer division or integer remainder operations'
[patent_app_type] => new
[patent_app_number] => 10/098151
[patent_app_country] => US
[patent_app_date] => 2002-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 7006
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 120
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0046/20030046672.pdf
[firstpage_image] =>[orig_patent_app_number] => 10098151
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/098151 | Development system of microprocessor for application program including integer division or integer remainder operations | Mar 14, 2002 | Issued |
Array
(
[id] => 704700
[patent_doc_number] => 07069285
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-27
[patent_title] => 'Decimation filter'
[patent_app_type] => utility
[patent_app_number] => 10/094852
[patent_app_country] => US
[patent_app_date] => 2002-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3102
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/069/07069285.pdf
[firstpage_image] =>[orig_patent_app_number] => 10094852
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/094852 | Decimation filter | Mar 10, 2002 | Issued |
Array
(
[id] => 6180600
[patent_doc_number] => 20020156820
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-24
[patent_title] => 'Frequency converter'
[patent_app_type] => new
[patent_app_number] => 10/090521
[patent_app_country] => US
[patent_app_date] => 2002-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7611
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0156/20020156820.pdf
[firstpage_image] =>[orig_patent_app_number] => 10090521
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/090521 | Frequency converter | Mar 3, 2002 | Issued |
Array
(
[id] => 1228799
[patent_doc_number] => 06701335
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-02
[patent_title] => 'Digital frequency response compensator and arbitrary response generator system'
[patent_app_type] => B2
[patent_app_number] => 10/090051
[patent_app_country] => US
[patent_app_date] => 2002-02-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 13367
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/701/06701335.pdf
[firstpage_image] =>[orig_patent_app_number] => 10090051
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/090051 | Digital frequency response compensator and arbitrary response generator system | Feb 26, 2002 | Issued |
Array
(
[id] => 6835958
[patent_doc_number] => 20030163504
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Addition circuit for accumulating redundant binary numbers'
[patent_app_type] => new
[patent_app_number] => 10/082152
[patent_app_country] => US
[patent_app_date] => 2002-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2954
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20030163504.pdf
[firstpage_image] =>[orig_patent_app_number] => 10082152
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/082152 | Addition circuit for accumulating redundant binary numbers | Feb 25, 2002 | Issued |
Array
(
[id] => 7173393
[patent_doc_number] => 20040078405
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-22
[patent_title] => 'Efficient implementation of a multidimensional fast fourier transform on a distributed-memory parallel multi-node computer'
[patent_app_type] => new
[patent_app_number] => 10/468998
[patent_app_country] => US
[patent_app_date] => 2003-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8117
[patent_no_of_claims] => 33
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 35
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0078/20040078405.pdf
[firstpage_image] =>[orig_patent_app_number] => 10468998
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/468998 | Efficient implementation of a multidimensional fast fourier transform on a distributed-memory parallel multi-node computer | Feb 24, 2002 | Issued |
Array
(
[id] => 6835957
[patent_doc_number] => 20030163503
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-08-28
[patent_title] => 'Method and apparatus for implementing signed multiplication of operands having differing bit widths without sign extension of the multiplicand'
[patent_app_type] => new
[patent_app_number] => 10/081431
[patent_app_country] => US
[patent_app_date] => 2002-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2959
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20030163503.pdf
[firstpage_image] =>[orig_patent_app_number] => 10081431
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/081431 | Method and apparatus for implementing signed multiplication of operands having differing bit widths without sign extension of the multiplicand | Feb 21, 2002 | Issued |
Array
(
[id] => 6810305
[patent_doc_number] => 20030200244
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-23
[patent_title] => 'Generation of mask-constrained floating-point addition and substraction test cases, and method and system therefor'
[patent_app_type] => new
[patent_app_number] => 10/078111
[patent_app_country] => US
[patent_app_date] => 2002-02-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 19781
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0200/20030200244.pdf
[firstpage_image] =>[orig_patent_app_number] => 10078111
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/078111 | Generation of mask-constrained floating-point addition and subtraction test cases, and method and system therefor | Feb 19, 2002 | Issued |
Array
(
[id] => 6558678
[patent_doc_number] => 20020138536
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-09-26
[patent_title] => 'Time-division type matrix calculator'
[patent_app_type] => new
[patent_app_number] => 10/060232
[patent_app_country] => US
[patent_app_date] => 2002-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4289
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0138/20020138536.pdf
[firstpage_image] =>[orig_patent_app_number] => 10060232
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/060232 | Time-division type matrix calculator | Jan 31, 2002 | Issued |