Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 785834 [patent_doc_number] => 06993545 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Digital filter with protection against overflow oscillation' [patent_app_type] => utility [patent_app_number] => 09/964081 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 43 [patent_no_of_words] => 16812 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993545.pdf [firstpage_image] =>[orig_patent_app_number] => 09964081 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964081
Digital filter with protection against overflow oscillation Sep 24, 2001 Issued
Array ( [id] => 933139 [patent_doc_number] => 06981013 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'Low power, minimal area tap multiplier' [patent_app_type] => utility [patent_app_number] => 09/963042 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8454 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981013.pdf [firstpage_image] =>[orig_patent_app_number] => 09963042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/963042
Low power, minimal area tap multiplier Sep 23, 2001 Issued
Array ( [id] => 6722166 [patent_doc_number] => 20030055856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-20 [patent_title] => 'Architecture component and method for performing discrete wavelet transforms' [patent_app_type] => new [patent_app_number] => 09/957292 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4885 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20030055856.pdf [firstpage_image] =>[orig_patent_app_number] => 09957292 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957292
Architecture component and method for performing discrete wavelet transforms Sep 18, 2001 Abandoned
Array ( [id] => 1422976 [patent_doc_number] => 06539409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-25 [patent_title] => 'Method for synthesizing linear finite state machines' [patent_app_type] => B2 [patent_app_number] => 09/957701 [patent_app_country] => US [patent_app_date] => 2001-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 31 [patent_no_of_words] => 5063 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/539/06539409.pdf [firstpage_image] =>[orig_patent_app_number] => 09957701 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957701
Method for synthesizing linear finite state machines Sep 17, 2001 Issued
Array ( [id] => 7628252 [patent_doc_number] => 06820108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method and apparatus to perform division in hardware' [patent_app_type] => B2 [patent_app_number] => 09/949331 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2513 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/820/06820108.pdf [firstpage_image] =>[orig_patent_app_number] => 09949331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/949331
Method and apparatus to perform division in hardware Sep 6, 2001 Issued
Array ( [id] => 685314 [patent_doc_number] => 07082450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Implementation of a transform and of a subsequent quantization' [patent_app_type] => utility [patent_app_number] => 09/943241 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 7934 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/082/07082450.pdf [firstpage_image] =>[orig_patent_app_number] => 09943241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943241
Implementation of a transform and of a subsequent quantization Aug 29, 2001 Issued
Array ( [id] => 1052474 [patent_doc_number] => 06862605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'True random number generator and entropy calculation device and method' [patent_app_type] => utility [patent_app_number] => 09/930072 [patent_app_country] => US [patent_app_date] => 2001-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5487 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862605.pdf [firstpage_image] =>[orig_patent_app_number] => 09930072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/930072
True random number generator and entropy calculation device and method Aug 14, 2001 Issued
Array ( [id] => 6839747 [patent_doc_number] => 20030037087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Apparatus and method for efficient modular exponentiation' [patent_app_type] => new [patent_app_number] => 09/929462 [patent_app_country] => US [patent_app_date] => 2001-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5727 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037087.pdf [firstpage_image] =>[orig_patent_app_number] => 09929462 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/929462
Apparatus and method for efficient modular exponentiation Aug 13, 2001 Issued
Array ( [id] => 7611399 [patent_doc_number] => 06904443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-07 [patent_title] => 'Harmonic-series filter' [patent_app_type] => utility [patent_app_number] => 09/928512 [patent_app_country] => US [patent_app_date] => 2001-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3203 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/904/06904443.pdf [firstpage_image] =>[orig_patent_app_number] => 09928512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/928512
Harmonic-series filter Aug 12, 2001 Issued
Array ( [id] => 6793253 [patent_doc_number] => 20030088597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Method and system for string representation of floating point numbers' [patent_app_type] => new [patent_app_number] => 09/920523 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2513 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088597.pdf [firstpage_image] =>[orig_patent_app_number] => 09920523 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920523
Method and system for string representation of floating point numbers Aug 1, 2001 Abandoned
Array ( [id] => 949902 [patent_doc_number] => 06963896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-08 [patent_title] => 'Method and system to implement an improved floating point adder with integrated adding and rounding' [patent_app_type] => utility [patent_app_number] => 09/919713 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 23586 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963896.pdf [firstpage_image] =>[orig_patent_app_number] => 09919713 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919713
Method and system to implement an improved floating point adder with integrated adding and rounding Jul 30, 2001 Issued
Array ( [id] => 6411936 [patent_doc_number] => 20020038202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Arithmetic unit' [patent_app_type] => new [patent_app_number] => 09/919482 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4452 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20020038202.pdf [firstpage_image] =>[orig_patent_app_number] => 09919482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919482
Arithmetic unit Jul 29, 2001 Issued
Array ( [id] => 6133482 [patent_doc_number] => 20020078110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-20 [patent_title] => 'Parallel counter and a logic circuit for performing multiplication' [patent_app_type] => new [patent_app_number] => 09/917257 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 13457 [patent_no_of_claims] => 149 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20020078110.pdf [firstpage_image] =>[orig_patent_app_number] => 09917257 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917257
Parallel counter and a logic circuit for performing multiplication Jul 26, 2001 Issued
Array ( [id] => 7613916 [patent_doc_number] => 06898615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Signal processing unit and signal processing method including using an exponent part and a mantissa part for power generation' [patent_app_type] => utility [patent_app_number] => 09/909971 [patent_app_country] => US [patent_app_date] => 2001-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5496 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898615.pdf [firstpage_image] =>[orig_patent_app_number] => 09909971 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909971
Signal processing unit and signal processing method including using an exponent part and a mantissa part for power generation Jul 22, 2001 Issued
Array ( [id] => 933133 [patent_doc_number] => 06981010 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-27 [patent_title] => 'System and method for generating psuedo-noise sequences' [patent_app_type] => utility [patent_app_number] => 09/906213 [patent_app_country] => US [patent_app_date] => 2001-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10965 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/981/06981010.pdf [firstpage_image] =>[orig_patent_app_number] => 09906213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/906213
System and method for generating psuedo-noise sequences Jul 16, 2001 Issued
Array ( [id] => 6736822 [patent_doc_number] => 20030014457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Method and apparatus for vector processing' [patent_app_type] => new [patent_app_number] => 09/905441 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6500 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20030014457.pdf [firstpage_image] =>[orig_patent_app_number] => 09905441 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/905441
Method and apparatus for vector processing Jul 12, 2001 Issued
Array ( [id] => 6001471 [patent_doc_number] => 20020029234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-07 [patent_title] => 'Recursive discrete fourier transformation apparatus' [patent_app_type] => new [patent_app_number] => 09/903573 [patent_app_country] => US [patent_app_date] => 2001-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 14044 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20020029234.pdf [firstpage_image] =>[orig_patent_app_number] => 09903573 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/903573
Recursive discrete fourier transformation apparatus Jul 12, 2001 Abandoned
Array ( [id] => 1459792 [patent_doc_number] => 06463451 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-08 [patent_title] => 'High speed digital signal processor' [patent_app_type] => B2 [patent_app_number] => 09/902603 [patent_app_country] => US [patent_app_date] => 2001-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7245 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463451.pdf [firstpage_image] =>[orig_patent_app_number] => 09902603 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/902603
High speed digital signal processor Jul 11, 2001 Issued
Array ( [id] => 6717223 [patent_doc_number] => 20030028571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-06 [patent_title] => 'Real-time method for bit-reversal of large size arrays' [patent_app_type] => new [patent_app_number] => 09/900153 [patent_app_country] => US [patent_app_date] => 2001-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4699 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20030028571.pdf [firstpage_image] =>[orig_patent_app_number] => 09900153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/900153
Real-time method for bit-reversal of large size arrays Jul 8, 2001 Issued
Array ( [id] => 626160 [patent_doc_number] => 07139788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-21 [patent_title] => 'Multiplication logic circuit' [patent_app_type] => utility [patent_app_number] => 09/898752 [patent_app_country] => US [patent_app_date] => 2001-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2668 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/139/07139788.pdf [firstpage_image] =>[orig_patent_app_number] => 09898752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/898752
Multiplication logic circuit Jul 2, 2001 Issued
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