Richard L Schilling

Array ( [id] => 6900401 [patent_doc_number] => 20010010077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'Computationally efficient modular multiplication method and apparatus' [patent_app_type] => new [patent_app_number] => 09/758782 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20010010077.pdf [firstpage_image] =>[orig_patent_app_number] => 09758782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1169155 [patent_doc_number] => 06766339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Method and system for efficient and accurate filtering and interpolation' [patent_app_type] => B2 [patent_app_number] => 09/757622 [patent_app_country] => US [patent_app_date] => 2001-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 8563 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/766/06766339.pdf [firstpage_image] =>[orig_patent_app_number] => 09757622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7118664 [patent_doc_number] => 20010001860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith' [patent_app_type] => new-utility [patent_app_number] => 09/758080 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6662 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001860.pdf [firstpage_image] =>[orig_patent_app_number] => 09758080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7118667 [patent_doc_number] => 20010001862 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith' [patent_app_type] => new-utility [patent_app_number] => 09/758071 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6655 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001862.pdf [firstpage_image] =>[orig_patent_app_number] => 09758071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7118665 [patent_doc_number] => 20010001861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith' [patent_app_type] => new-utility [patent_app_number] => 09/757978 [patent_app_country] => US [patent_app_date] => 2001-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6665 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001861.pdf [firstpage_image] =>[orig_patent_app_number] => 09757978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1566888 [patent_doc_number] => 06438567 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-20 [patent_title] => 'Method for selective filtering' [patent_app_type] => B2 [patent_app_number] => 09/752922 [patent_app_country] => US [patent_app_date] => 2001-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4152 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438567.pdf [firstpage_image] =>[orig_patent_app_number] => 09752922 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6889835 [patent_doc_number] => 20010025290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-27 [patent_title] => 'Nonrecursive digital filter and method for calculating the coefficients of the filter' [patent_app_type] => new [patent_app_number] => 09/752923 [patent_app_country] => US [patent_app_date] => 2001-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2709 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20010025290.pdf [firstpage_image] =>[orig_patent_app_number] => 09752923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5925967 [patent_doc_number] => 20020116434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-22 [patent_title] => 'Apparatus and method for performing multiplication operations' [patent_app_type] => new [patent_app_number] => 09/748152 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8347 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20020116434.pdf [firstpage_image] =>[orig_patent_app_number] => 09748152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1129312 [patent_doc_number] => 06795842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Method and apparatus for comparing two binary numbers with a power-of-two threshold' [patent_app_type] => B2 [patent_app_number] => 09/749081 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4234 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/795/06795842.pdf [firstpage_image] =>[orig_patent_app_number] => 09749081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5890197 [patent_doc_number] => 20020013800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-31 [patent_title] => 'Method and apparatus for performing single-cycle addition or subtraction and comparison in redundant form arithmetic' [patent_app_type] => new [patent_app_number] => 09/746940 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6069 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20020013800.pdf [firstpage_image] =>[orig_patent_app_number] => 09746940 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6114791 [patent_doc_number] => 20020174157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Method and apparatus for performing equality comparison in redundant form arithmetic' [patent_app_type] => new [patent_app_number] => 09/746771 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 8561 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20020174157.pdf [firstpage_image] =>[orig_patent_app_number] => 09746771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1180432 [patent_doc_number] => 06754689 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Method and apparatus for performing subtraction in redundant form arithmetic' [patent_app_type] => B2 [patent_app_number] => 09/745697 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 4751 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754689.pdf [firstpage_image] =>[orig_patent_app_number] => 09745697 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1297732 [patent_doc_number] => 06631389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-07 [patent_title] => 'Apparatus for performing packed shift operations' [patent_app_type] => B2 [patent_app_number] => 09/747122 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 13519 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/631/06631389.pdf [firstpage_image] =>[orig_patent_app_number] => 09747122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6387646 [patent_doc_number] => 20020120656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-29 [patent_title] => 'Practical pseudo-asynchronous filter architecture' [patent_app_type] => new [patent_app_number] => 09/739331 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6895 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20020120656.pdf [firstpage_image] =>[orig_patent_app_number] => 09739331 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7105702 [patent_doc_number] => 20010004740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'Method of performing operations with a variable arithmetic' [patent_app_type] => new-utility [patent_app_number] => 09/738132 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2963 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004740.pdf [firstpage_image] =>[orig_patent_app_number] => 09738132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1097102 [patent_doc_number] => 06826586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Method for efficient computation of point doubling operation of elliptic curve point scalar multiplication over finite fields F(2m)' [patent_app_type] => B2 [patent_app_number] => 09/738571 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4225 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826586.pdf [firstpage_image] =>[orig_patent_app_number] => 09738571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1192130 [patent_doc_number] => 06735608 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-11 [patent_title] => 'Data interpolation method' [patent_app_type] => B1 [patent_app_number] => 09/719622 [patent_app_country] => US [patent_app_date] => 2000-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 23 [patent_no_of_words] => 4963 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/735/06735608.pdf [firstpage_image] =>[orig_patent_app_number] => 09719622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1143050 [patent_doc_number] => 06785700 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Implementation of wavelet functions in hardware' [patent_app_type] => B2 [patent_app_number] => 09/736891 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 8085 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/785/06785700.pdf [firstpage_image] =>[orig_patent_app_number] => 09736891 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1200751 [patent_doc_number] => 06728739 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'Data calculating device and method for processing data in data block form' [patent_app_type] => B1 [patent_app_number] => 09/719351 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10913 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/728/06728739.pdf [firstpage_image] =>[orig_patent_app_number] => 09719351 [rel_patent_id] =>[rel_patent_doc_number] =>)