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Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1399951 [patent_doc_number] => 06564236 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Device and associated method for calculating the direct or inverse fourier transform of the product of a complex symbol times a complex sinusoidal waveform' [patent_app_type] => B1 [patent_app_number] => 09/491001 [patent_app_country] => US [patent_app_date] => 2000-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 6359 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564236.pdf [firstpage_image] =>[orig_patent_app_number] => 09491001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/491001
Device and associated method for calculating the direct or inverse fourier transform of the product of a complex symbol times a complex sinusoidal waveform Jan 24, 2000 Issued
Array ( [id] => 1424604 [patent_doc_number] => 06535898 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Fast floating-point truncation to integer form' [patent_app_type] => B1 [patent_app_number] => 09/490247 [patent_app_country] => US [patent_app_date] => 2000-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6745 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535898.pdf [firstpage_image] =>[orig_patent_app_number] => 09490247 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/490247
Fast floating-point truncation to integer form Jan 23, 2000 Issued
Array ( [id] => 1431182 [patent_doc_number] => 06519619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Circuit for generating periodic function' [patent_app_type] => B1 [patent_app_number] => 09/488531 [patent_app_country] => US [patent_app_date] => 2000-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7066 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/519/06519619.pdf [firstpage_image] =>[orig_patent_app_number] => 09488531 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/488531
Circuit for generating periodic function Jan 20, 2000 Issued
Array ( [id] => 7630057 [patent_doc_number] => 06636882 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Means and method for performing multiplication' [patent_app_type] => B1 [patent_app_number] => 09/482623 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4288 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636882.pdf [firstpage_image] =>[orig_patent_app_number] => 09482623 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/482623
Means and method for performing multiplication Jan 13, 2000 Issued
Array ( [id] => 1364485 [patent_doc_number] => 06581084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Circuit for multiplication in a Galois field' [patent_app_type] => B1 [patent_app_number] => 09/483343 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3685 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/581/06581084.pdf [firstpage_image] =>[orig_patent_app_number] => 09483343 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/483343
Circuit for multiplication in a Galois field Jan 13, 2000 Issued
Array ( [id] => 1410487 [patent_doc_number] => 06553399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Method and circuit for envelope detection using a peel cone approximation' [patent_app_type] => B1 [patent_app_number] => 09/481141 [patent_app_country] => US [patent_app_date] => 2000-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2080 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553399.pdf [firstpage_image] =>[orig_patent_app_number] => 09481141 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481141
Method and circuit for envelope detection using a peel cone approximation Jan 11, 2000 Issued
Array ( [id] => 1429355 [patent_doc_number] => 06510442 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'System and method for improved digital differential analyzer' [patent_app_type] => B1 [patent_app_number] => 09/481223 [patent_app_country] => US [patent_app_date] => 2000-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/510/06510442.pdf [firstpage_image] =>[orig_patent_app_number] => 09481223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481223
System and method for improved digital differential analyzer Jan 11, 2000 Issued
Array ( [id] => 1214087 [patent_doc_number] => 06714957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'System and method for efficient processing of denormal results as hardware exceptions' [patent_app_type] => B1 [patent_app_number] => 09/477092 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/714/06714957.pdf [firstpage_image] =>[orig_patent_app_number] => 09477092 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477092
System and method for efficient processing of denormal results as hardware exceptions Jan 3, 2000 Issued
Array ( [id] => 1405608 [patent_doc_number] => 06560624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Method of executing each of division and remainder instructions and data processing device using the method' [patent_app_type] => B1 [patent_app_number] => 09/477001 [patent_app_country] => US [patent_app_date] => 2000-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 7441 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560624.pdf [firstpage_image] =>[orig_patent_app_number] => 09477001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/477001
Method of executing each of division and remainder instructions and data processing device using the method Jan 2, 2000 Issued
Array ( [id] => 1352409 [patent_doc_number] => 06594680 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Psuedo-random noise sequence generating system' [patent_app_type] => B1 [patent_app_number] => 09/475932 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2871 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594680.pdf [firstpage_image] =>[orig_patent_app_number] => 09475932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475932
Psuedo-random noise sequence generating system Dec 29, 1999 Issued
Array ( [id] => 1384961 [patent_doc_number] => 06571269 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Noise-tolerant digital adder circuit and method' [patent_app_type] => B1 [patent_app_number] => 09/475422 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 26 [patent_no_of_words] => 8133 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571269.pdf [firstpage_image] =>[orig_patent_app_number] => 09475422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/475422
Noise-tolerant digital adder circuit and method Dec 29, 1999 Issued
Array ( [id] => 1196672 [patent_doc_number] => 06732136 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Differential, low voltage swing reducer' [patent_app_type] => B1 [patent_app_number] => 09/471201 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6034 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732136.pdf [firstpage_image] =>[orig_patent_app_number] => 09471201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471201
Differential, low voltage swing reducer Dec 22, 1999 Issued
Array ( [id] => 1347030 [patent_doc_number] => 06598065 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method for achieving correctly rounded quotients in algorithms based on fused multiply-accumulate without requiring the intermediate calculation of a correctly rounded reciprocal' [patent_app_type] => B1 [patent_app_number] => 09/471651 [patent_app_country] => US [patent_app_date] => 1999-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2876 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598065.pdf [firstpage_image] =>[orig_patent_app_number] => 09471651 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/471651
Method for achieving correctly rounded quotients in algorithms based on fused multiply-accumulate without requiring the intermediate calculation of a correctly rounded reciprocal Dec 22, 1999 Issued
Array ( [id] => 1431774 [patent_doc_number] => 06516333 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Sticky bit value predicting circuit' [patent_app_type] => B1 [patent_app_number] => 09/468852 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3766 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516333.pdf [firstpage_image] =>[orig_patent_app_number] => 09468852 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/468852
Sticky bit value predicting circuit Dec 20, 1999 Issued
Array ( [id] => 1416397 [patent_doc_number] => 06532486 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Apparatus and method for saturating data in register' [patent_app_type] => B1 [patent_app_number] => 09/464731 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4702 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/532/06532486.pdf [firstpage_image] =>[orig_patent_app_number] => 09464731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/464731
Apparatus and method for saturating data in register Dec 14, 1999 Issued
Array ( [id] => 1410433 [patent_doc_number] => 06553396 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Filter bank constituting method and filter bank apparatus' [patent_app_type] => B1 [patent_app_number] => 09/457822 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8894 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/553/06553396.pdf [firstpage_image] =>[orig_patent_app_number] => 09457822 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/457822
Filter bank constituting method and filter bank apparatus Dec 8, 1999 Issued
Array ( [id] => 1540390 [patent_doc_number] => 06490608 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Fast parallel multiplier implemented with improved tree reduction schemes' [patent_app_type] => B1 [patent_app_number] => 09/458542 [patent_app_country] => US [patent_app_date] => 1999-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6476 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490608.pdf [firstpage_image] =>[orig_patent_app_number] => 09458542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/458542
Fast parallel multiplier implemented with improved tree reduction schemes Dec 8, 1999 Issued
Array ( [id] => 4324470 [patent_doc_number] => 06253223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Robust random number generator' [patent_app_type] => 1 [patent_app_number] => 9/455951 [patent_app_country] => US [patent_app_date] => 1999-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3421 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253223.pdf [firstpage_image] =>[orig_patent_app_number] => 455951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/455951
Robust random number generator Dec 6, 1999 Issued
Array ( [id] => 1429973 [patent_doc_number] => 06526427 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Method of mask calculation for generation of shifted pseudo-noise (PN) sequence' [patent_app_type] => B1 [patent_app_number] => 09/455001 [patent_app_country] => US [patent_app_date] => 1999-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6928 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526427.pdf [firstpage_image] =>[orig_patent_app_number] => 09455001 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/455001
Method of mask calculation for generation of shifted pseudo-noise (PN) sequence Dec 5, 1999 Issued
Array ( [id] => 1431769 [patent_doc_number] => 06516330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Counting set bits in data words' [patent_app_type] => B1 [patent_app_number] => 09/452681 [patent_app_country] => US [patent_app_date] => 1999-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7111 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516330.pdf [firstpage_image] =>[orig_patent_app_number] => 09452681 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452681
Counting set bits in data words Nov 30, 1999 Issued
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