Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4297748 [patent_doc_number] => 06282556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'High performance pipelined data path for a media processor' [patent_app_type] => 1 [patent_app_number] => 9/451669 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 11252 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282556.pdf [firstpage_image] =>[orig_patent_app_number] => 451669 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/451669
High performance pipelined data path for a media processor Nov 29, 1999 Issued
Array ( [id] => 1484701 [patent_doc_number] => 06453330 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'High-precision bilinear interpolation' [patent_app_type] => B1 [patent_app_number] => 09/449012 [patent_app_country] => US [patent_app_date] => 1999-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6517 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453330.pdf [firstpage_image] =>[orig_patent_app_number] => 09449012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/449012
High-precision bilinear interpolation Nov 23, 1999 Issued
Array ( [id] => 7631644 [patent_doc_number] => 06665693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-16 [patent_title] => 'Digital signal processing circuits, systems, and methods implementing approximations for a reciprocal' [patent_app_type] => B1 [patent_app_number] => 09/447461 [patent_app_country] => US [patent_app_date] => 1999-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6160 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/665/06665693.pdf [firstpage_image] =>[orig_patent_app_number] => 09447461 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/447461
Digital signal processing circuits, systems, and methods implementing approximations for a reciprocal Nov 21, 1999 Issued
Array ( [id] => 1430993 [patent_doc_number] => 06523054 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Galois field arithmetic processor' [patent_app_type] => B1 [patent_app_number] => 09/437473 [patent_app_country] => US [patent_app_date] => 1999-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7695 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523054.pdf [firstpage_image] =>[orig_patent_app_number] => 09437473 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/437473
Galois field arithmetic processor Nov 9, 1999 Issued
Array ( [id] => 1236062 [patent_doc_number] => 06694344 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Examination of residues of data-conversions' [patent_app_type] => B1 [patent_app_number] => 09/436851 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1614 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/694/06694344.pdf [firstpage_image] =>[orig_patent_app_number] => 09436851 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436851
Examination of residues of data-conversions Nov 8, 1999 Issued
Array ( [id] => 1414718 [patent_doc_number] => 06549927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Circuit and method for summing multiple binary vectors' [patent_app_type] => B1 [patent_app_number] => 09/436773 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549927.pdf [firstpage_image] =>[orig_patent_app_number] => 09436773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436773
Circuit and method for summing multiple binary vectors Nov 7, 1999 Issued
Array ( [id] => 1557287 [patent_doc_number] => 06401107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Method and processor for reducing computational error in a processor having no rounding support' [patent_app_type] => B1 [patent_app_number] => 09/433632 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3573 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401107.pdf [firstpage_image] =>[orig_patent_app_number] => 09433632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/433632
Method and processor for reducing computational error in a processor having no rounding support Nov 2, 1999 Issued
Array ( [id] => 671364 [patent_doc_number] => 07096240 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-22 [patent_title] => 'Channel coupling for an AC-3 encoder' [patent_app_type] => utility [patent_app_number] => 10/129041 [patent_app_country] => US [patent_app_date] => 1999-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/096/07096240.pdf [firstpage_image] =>[orig_patent_app_number] => 10129041 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/129041
Channel coupling for an AC-3 encoder Oct 29, 1999 Issued
Array ( [id] => 1428590 [patent_doc_number] => 06513055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Apparatus and method for data width reduction in automotive systems' [patent_app_type] => B1 [patent_app_number] => 09/430762 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2724 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/513/06513055.pdf [firstpage_image] =>[orig_patent_app_number] => 09430762 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430762
Apparatus and method for data width reduction in automotive systems Oct 28, 1999 Issued
Array ( [id] => 1573621 [patent_doc_number] => 06499045 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Implementation of a two-dimensional wavelet transform' [patent_app_type] => B1 [patent_app_number] => 09/422923 [patent_app_country] => US [patent_app_date] => 1999-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 5091 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/499/06499045.pdf [firstpage_image] =>[orig_patent_app_number] => 09422923 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/422923
Implementation of a two-dimensional wavelet transform Oct 20, 1999 Issued
Array ( [id] => 1580082 [patent_doc_number] => 06470369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Euclid mutual division arithmetic circuit and processing circuit' [patent_app_type] => B1 [patent_app_number] => 09/421672 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470369.pdf [firstpage_image] =>[orig_patent_app_number] => 09421672 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421672
Euclid mutual division arithmetic circuit and processing circuit Oct 19, 1999 Issued
Array ( [id] => 1540384 [patent_doc_number] => 06490607 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Shared FP and SIMD 3D multiplier' [patent_app_type] => B1 [patent_app_number] => 09/416401 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 12592 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490607.pdf [firstpage_image] =>[orig_patent_app_number] => 09416401 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416401
Shared FP and SIMD 3D multiplier Oct 11, 1999 Issued
Array ( [id] => 1356203 [patent_doc_number] => 06591281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Numerical data processing apparatus and numerical data processing method' [patent_app_type] => B1 [patent_app_number] => 09/415501 [patent_app_country] => US [patent_app_date] => 1999-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8308 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591281.pdf [firstpage_image] =>[orig_patent_app_number] => 09415501 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415501
Numerical data processing apparatus and numerical data processing method Oct 11, 1999 Issued
Array ( [id] => 1526319 [patent_doc_number] => 06353843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'High performance universal multiplier circuit' [patent_app_type] => B1 [patent_app_number] => 09/415485 [patent_app_country] => US [patent_app_date] => 1999-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 24 [patent_no_of_words] => 10090 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353843.pdf [firstpage_image] =>[orig_patent_app_number] => 09415485 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/415485
High performance universal multiplier circuit Oct 7, 1999 Issued
Array ( [id] => 1375995 [patent_doc_number] => 06578058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'System and method for comparing values from target systems' [patent_app_type] => B1 [patent_app_number] => 09/413731 [patent_app_country] => US [patent_app_date] => 1999-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4299 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578058.pdf [firstpage_image] =>[orig_patent_app_number] => 09413731 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/413731
System and method for comparing values from target systems Oct 5, 1999 Issued
Array ( [id] => 1524722 [patent_doc_number] => 06415310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Remainder calculating method, modular-multiplication method, remainder calculating apparatus, modular-multiplication apparatus and recording medium' [patent_app_type] => B1 [patent_app_number] => 09/412502 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 6783 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415310.pdf [firstpage_image] =>[orig_patent_app_number] => 09412502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412502
Remainder calculating method, modular-multiplication method, remainder calculating apparatus, modular-multiplication apparatus and recording medium Oct 4, 1999 Issued
Array ( [id] => 1432332 [patent_doc_number] => 06505224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'System and computer-implemented method for performing multi-stage fast Walsh transform' [patent_app_type] => B1 [patent_app_number] => 09/408463 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5414 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505224.pdf [firstpage_image] =>[orig_patent_app_number] => 09408463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408463
System and computer-implemented method for performing multi-stage fast Walsh transform Sep 28, 1999 Issued
Array ( [id] => 1604402 [patent_doc_number] => 06434588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Binary counter with low power consumption' [patent_app_type] => B1 [patent_app_number] => 09/407742 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2534 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434588.pdf [firstpage_image] =>[orig_patent_app_number] => 09407742 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407742
Binary counter with low power consumption Sep 27, 1999 Issued
Array ( [id] => 7642461 [patent_doc_number] => 06430585 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Noise tolerant conductance-based logic gate and methods of operation and manufacturing thereof' [patent_app_type] => B1 [patent_app_number] => 09/406367 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7074 [patent_no_of_claims] => 80 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430585.pdf [firstpage_image] =>[orig_patent_app_number] => 09406367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406367
Noise tolerant conductance-based logic gate and methods of operation and manufacturing thereof Sep 27, 1999 Issued
Array ( [id] => 1566908 [patent_doc_number] => 06438572 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Adder having reduced number of internal layers and method of operation thereof' [patent_app_type] => B1 [patent_app_number] => 09/407598 [patent_app_country] => US [patent_app_date] => 1999-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4440 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438572.pdf [firstpage_image] =>[orig_patent_app_number] => 09407598 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/407598
Adder having reduced number of internal layers and method of operation thereof Sep 27, 1999 Issued
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