Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4422822 [patent_doc_number] => 06311200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Reconfigurable program sum of products generator' [patent_app_type] => 1 [patent_app_number] => 9/401313 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 3547 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311200.pdf [firstpage_image] =>[orig_patent_app_number] => 401313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401313
Reconfigurable program sum of products generator Sep 22, 1999 Issued
Array ( [id] => 1521556 [patent_doc_number] => 06502119 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'High speed microprocessor zero detection circuit with 32-bit and 64-bit modes' [patent_app_type] => B1 [patent_app_number] => 09/400052 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2194 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502119.pdf [firstpage_image] =>[orig_patent_app_number] => 09400052 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400052
High speed microprocessor zero detection circuit with 32-bit and 64-bit modes Sep 20, 1999 Issued
Array ( [id] => 1566896 [patent_doc_number] => 06438569 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Sums of production datapath' [patent_app_type] => B1 [patent_app_number] => 09/399981 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 24 [patent_no_of_words] => 22217 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/438/06438569.pdf [firstpage_image] =>[orig_patent_app_number] => 09399981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399981
Sums of production datapath Sep 19, 1999 Issued
Array ( [id] => 1432329 [patent_doc_number] => 06505221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'FIR filter utilizing programmable shifter' [patent_app_type] => B1 [patent_app_number] => 09/400700 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 6067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505221.pdf [firstpage_image] =>[orig_patent_app_number] => 09400700 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400700
FIR filter utilizing programmable shifter Sep 19, 1999 Issued
Array ( [id] => 1428658 [patent_doc_number] => 06529930 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Methods and apparatus for performing a signed saturation operation' [patent_app_type] => B1 [patent_app_number] => 09/393591 [patent_app_country] => US [patent_app_date] => 1999-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5981 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529930.pdf [firstpage_image] =>[orig_patent_app_number] => 09393591 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/393591
Methods and apparatus for performing a signed saturation operation Sep 8, 1999 Issued
Array ( [id] => 1424629 [patent_doc_number] => 06535900 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Accumulation saturation by means of feedback' [patent_app_type] => B1 [patent_app_number] => 09/391823 [patent_app_country] => US [patent_app_date] => 1999-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2927 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535900.pdf [firstpage_image] =>[orig_patent_app_number] => 09391823 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/391823
Accumulation saturation by means of feedback Sep 7, 1999 Issued
Array ( [id] => 7642458 [patent_doc_number] => 06430588 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Apparatus and method for elliptic-curve multiplication and recording medium having recorded thereon a program for implementing the method' [patent_app_type] => B1 [patent_app_number] => 09/389233 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 50 [patent_no_of_words] => 16902 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430588.pdf [firstpage_image] =>[orig_patent_app_number] => 09389233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389233
Apparatus and method for elliptic-curve multiplication and recording medium having recorded thereon a program for implementing the method Sep 2, 1999 Issued
Array ( [id] => 1431778 [patent_doc_number] => 06516335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Incrementer/decrementer having a reduced fanout architecture' [patent_app_type] => B1 [patent_app_number] => 09/386869 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5780 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516335.pdf [firstpage_image] =>[orig_patent_app_number] => 09386869 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386869
Incrementer/decrementer having a reduced fanout architecture Aug 30, 1999 Issued
Array ( [id] => 1430989 [patent_doc_number] => 06523053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-18 [patent_title] => 'Method and apparatus for dividing long polynomial expression in finite field' [patent_app_type] => B1 [patent_app_number] => 09/383792 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5855 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/523/06523053.pdf [firstpage_image] =>[orig_patent_app_number] => 09383792 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/383792
Method and apparatus for dividing long polynomial expression in finite field Aug 25, 1999 Issued
Array ( [id] => 1459788 [patent_doc_number] => 06463450 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method and apparatus for the location of the peak of a function using a filter bank' [patent_app_type] => B1 [patent_app_number] => 09/384111 [patent_app_country] => US [patent_app_date] => 1999-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3370 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463450.pdf [firstpage_image] =>[orig_patent_app_number] => 09384111 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/384111
Method and apparatus for the location of the peak of a function using a filter bank Aug 25, 1999 Issued
Array ( [id] => 1580067 [patent_doc_number] => 06470365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Method and architecture for complex datapath decimation and channel filtering' [patent_app_type] => B1 [patent_app_number] => 09/378932 [patent_app_country] => US [patent_app_date] => 1999-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 5639 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470365.pdf [firstpage_image] =>[orig_patent_app_number] => 09378932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/378932
Method and architecture for complex datapath decimation and channel filtering Aug 22, 1999 Issued
Array ( [id] => 1484709 [patent_doc_number] => 06453332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Method and apparatus for performing plural matrix multiplication operations' [patent_app_type] => B1 [patent_app_number] => 09/378041 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5590 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/453/06453332.pdf [firstpage_image] =>[orig_patent_app_number] => 09378041 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/378041
Method and apparatus for performing plural matrix multiplication operations Aug 19, 1999 Issued
Array ( [id] => 1365595 [patent_doc_number] => 06584482 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Multiplier array processing system with enhanced utilization at lower precision' [patent_app_type] => B1 [patent_app_number] => 09/377182 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5431 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/584/06584482.pdf [firstpage_image] =>[orig_patent_app_number] => 09377182 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377182
Multiplier array processing system with enhanced utilization at lower precision Aug 18, 1999 Issued
Array ( [id] => 1540380 [patent_doc_number] => 06490606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls' [patent_app_type] => B1 [patent_app_number] => 09/377683 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 7397 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490606.pdf [firstpage_image] =>[orig_patent_app_number] => 09377683 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377683
Rounding denormalized numbers in a pipelined floating point unit without pipeline stalls Aug 18, 1999 Issued
Array ( [id] => 1183138 [patent_doc_number] => 06751641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Time domain data converter with output frequency domain conversion' [patent_app_type] => B1 [patent_app_number] => 09/376761 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5867 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751641.pdf [firstpage_image] =>[orig_patent_app_number] => 09376761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376761
Time domain data converter with output frequency domain conversion Aug 16, 1999 Issued
Array ( [id] => 1462301 [patent_doc_number] => 06427160 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method and system for testing floating point logic' [patent_app_type] => B1 [patent_app_number] => 09/372183 [patent_app_country] => US [patent_app_date] => 1999-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9531 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427160.pdf [firstpage_image] =>[orig_patent_app_number] => 09372183 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/372183
Method and system for testing floating point logic Aug 9, 1999 Issued
Array ( [id] => 4421437 [patent_doc_number] => 06272511 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Weightless binary N-tuple thresholding hierarchies' [patent_app_type] => 1 [patent_app_number] => 9/366568 [patent_app_country] => US [patent_app_date] => 1999-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 2712 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272511.pdf [firstpage_image] =>[orig_patent_app_number] => 366568 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/366568
Weightless binary N-tuple thresholding hierarchies Aug 3, 1999 Issued
Array ( [id] => 1532865 [patent_doc_number] => 06480869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'Random-number generating circuit, non-contact IC card having random-number generating circuit, reader/writer, and method of testing an apparatus having the random generating circuit' [patent_app_type] => B1 [patent_app_number] => 09/364031 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7659 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480869.pdf [firstpage_image] =>[orig_patent_app_number] => 09364031 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364031
Random-number generating circuit, non-contact IC card having random-number generating circuit, reader/writer, and method of testing an apparatus having the random generating circuit Jul 29, 1999 Issued
Array ( [id] => 897467 [patent_doc_number] => 07346643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-18 [patent_title] => 'Processor with improved accuracy for multiply-add operations' [patent_app_type] => utility [patent_app_number] => 09/364512 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 9191 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/346/07346643.pdf [firstpage_image] =>[orig_patent_app_number] => 09364512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364512
Processor with improved accuracy for multiply-add operations Jul 29, 1999 Issued
Array ( [id] => 1420551 [patent_doc_number] => 06542916 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-01 [patent_title] => 'Data processing apparatus and method for applying floating-point operations to first, second and third operands' [patent_app_type] => B1 [patent_app_number] => 09/362182 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7444 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/542/06542916.pdf [firstpage_image] =>[orig_patent_app_number] => 09362182 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362182
Data processing apparatus and method for applying floating-point operations to first, second and third operands Jul 27, 1999 Issued
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