Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4426754 [patent_doc_number] => 06195670 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Smart modular electronic machine' [patent_app_type] => 1 [patent_app_number] => 9/360078 [patent_app_country] => US [patent_app_date] => 1999-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5392 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/195/06195670.pdf [firstpage_image] =>[orig_patent_app_number] => 360078 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/360078
Smart modular electronic machine Jul 22, 1999 Issued
Array ( [id] => 4334173 [patent_doc_number] => 06243728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Partitioned shift right logic circuit having rounding support' [patent_app_type] => 1 [patent_app_number] => 9/351273 [patent_app_country] => US [patent_app_date] => 1999-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 14 [patent_no_of_words] => 8489 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/243/06243728.pdf [firstpage_image] =>[orig_patent_app_number] => 351273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/351273
Partitioned shift right logic circuit having rounding support Jul 11, 1999 Issued
Array ( [id] => 1480642 [patent_doc_number] => 06389444 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Adder apparatus having single adder for 1 and 2 functions' [patent_app_type] => B1 [patent_app_number] => 09/348482 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3699 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389444.pdf [firstpage_image] =>[orig_patent_app_number] => 09348482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348482
Adder apparatus having single adder for 1 and 2 functions Jul 6, 1999 Issued
Array ( [id] => 7645967 [patent_doc_number] => 06477555 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-05 [patent_title] => 'Method and apparatus for performing rapid convolution' [patent_app_type] => B1 [patent_app_number] => 09/349263 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 9 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/477/06477555.pdf [firstpage_image] =>[orig_patent_app_number] => 09349263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/349263
Method and apparatus for performing rapid convolution Jul 6, 1999 Issued
Array ( [id] => 1601784 [patent_doc_number] => 06385633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Method and apparatus for computing complex phase' [patent_app_type] => B1 [patent_app_number] => 09/343421 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1697 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385633.pdf [firstpage_image] =>[orig_patent_app_number] => 09343421 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343421
Method and apparatus for computing complex phase Jun 29, 1999 Issued
Array ( [id] => 1489962 [patent_doc_number] => 06366938 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Reduced power matched filter using precomputation' [patent_app_type] => B1 [patent_app_number] => 09/343468 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9770 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366938.pdf [firstpage_image] =>[orig_patent_app_number] => 09343468 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/343468
Reduced power matched filter using precomputation Jun 29, 1999 Issued
Array ( [id] => 1602043 [patent_doc_number] => 06493737 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method and circuit for computing the discrete cosine transform (DCT) in microcontrollers' [patent_app_type] => B1 [patent_app_number] => 09/342601 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2389 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493737.pdf [firstpage_image] =>[orig_patent_app_number] => 09342601 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342601
Method and circuit for computing the discrete cosine transform (DCT) in microcontrollers Jun 28, 1999 Issued
Array ( [id] => 1601780 [patent_doc_number] => 06385632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Fast CORDIC algorithm with sine governed termination' [patent_app_type] => B1 [patent_app_number] => 09/336393 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 13455 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/385/06385632.pdf [firstpage_image] =>[orig_patent_app_number] => 09336393 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336393
Fast CORDIC algorithm with sine governed termination Jun 17, 1999 Issued
Array ( [id] => 1552521 [patent_doc_number] => 06446107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Circuitry for performing operations on binary numbers' [patent_app_type] => B1 [patent_app_number] => 09/336603 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 8557 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446107.pdf [firstpage_image] =>[orig_patent_app_number] => 09336603 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/336603
Circuitry for performing operations on binary numbers Jun 17, 1999 Issued
Array ( [id] => 1512992 [patent_doc_number] => 06442582 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Multiplier carry bit compression apparatus and method' [patent_app_type] => B1 [patent_app_number] => 09/335351 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2469 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442582.pdf [firstpage_image] =>[orig_patent_app_number] => 09335351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335351
Multiplier carry bit compression apparatus and method Jun 16, 1999 Issued
Array ( [id] => 1438580 [patent_doc_number] => 06356926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Device and method for calculating FFT' [patent_app_type] => B1 [patent_app_number] => 09/284752 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6161 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356926.pdf [firstpage_image] =>[orig_patent_app_number] => 09284752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/284752
Device and method for calculating FFT Jun 16, 1999 Issued
Array ( [id] => 6050975 [patent_doc_number] => 20020169811 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'DATA PROCESSOR ARCHITECTURE AND INSTRUCTION FORMAT FOR INCREASED EFFICIENCY' [patent_app_type] => new [patent_app_number] => 09/333903 [patent_app_country] => US [patent_app_date] => 1999-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3293 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20020169811.pdf [firstpage_image] =>[orig_patent_app_number] => 09333903 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333903
Data processor architecture and instruction format for increased efficiency Jun 15, 1999 Issued
Array ( [id] => 1538766 [patent_doc_number] => 06411979 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Complex number multiplier circuit' [patent_app_type] => B1 [patent_app_number] => 09/333071 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4036 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411979.pdf [firstpage_image] =>[orig_patent_app_number] => 09333071 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333071
Complex number multiplier circuit Jun 13, 1999 Issued
Array ( [id] => 1604401 [patent_doc_number] => 06434587 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Fast 16-B early termination implementation for 32-B multiply-accumulate unit' [patent_app_type] => B1 [patent_app_number] => 09/333153 [patent_app_country] => US [patent_app_date] => 1999-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 4987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434587.pdf [firstpage_image] =>[orig_patent_app_number] => 09333153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333153
Fast 16-B early termination implementation for 32-B multiply-accumulate unit Jun 13, 1999 Issued
Array ( [id] => 1452020 [patent_doc_number] => 06370557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Processing apparatus and method of the same' [patent_app_type] => B1 [patent_app_number] => 09/326693 [patent_app_country] => US [patent_app_date] => 1999-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9148 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370557.pdf [firstpage_image] =>[orig_patent_app_number] => 09326693 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/326693
Processing apparatus and method of the same Jun 6, 1999 Issued
Array ( [id] => 1592037 [patent_doc_number] => 06360242 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Summing circuit with high precision' [patent_app_type] => B1 [patent_app_number] => 09/323941 [patent_app_country] => US [patent_app_date] => 1999-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5785 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360242.pdf [firstpage_image] =>[orig_patent_app_number] => 09323941 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323941
Summing circuit with high precision Jun 1, 1999 Issued
Array ( [id] => 1538762 [patent_doc_number] => 06411978 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Mechanism for block floating point FFT hardware support on a fixed point digital signal processor' [patent_app_type] => B1 [patent_app_number] => 09/318632 [patent_app_country] => US [patent_app_date] => 1999-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4555 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411978.pdf [firstpage_image] =>[orig_patent_app_number] => 09318632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/318632
Mechanism for block floating point FFT hardware support on a fixed point digital signal processor May 25, 1999 Issued
Array ( [id] => 1552499 [patent_doc_number] => 06446102 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method and device for high speed scale conversion' [patent_app_type] => B1 [patent_app_number] => 09/316892 [patent_app_country] => US [patent_app_date] => 1999-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3089 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446102.pdf [firstpage_image] =>[orig_patent_app_number] => 09316892 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316892
Method and device for high speed scale conversion May 20, 1999 Issued
Array ( [id] => 1512979 [patent_doc_number] => 06442579 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-27 [patent_title] => 'Low power linear feedback shift registers' [patent_app_type] => B1 [patent_app_number] => 09/310753 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2420 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/442/06442579.pdf [firstpage_image] =>[orig_patent_app_number] => 09310753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/310753
Low power linear feedback shift registers May 12, 1999 Issued
Array ( [id] => 1196646 [patent_doc_number] => 06732126 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'High performance datapath unit for behavioral data transmission and reception' [patent_app_type] => B1 [patent_app_number] => 09/307072 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8274 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732126.pdf [firstpage_image] =>[orig_patent_app_number] => 09307072 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307072
High performance datapath unit for behavioral data transmission and reception May 6, 1999 Issued
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