Richard L Schilling

Array ( [id] => 1553629 [patent_doc_number] => 06347326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'N bit by M bit multiplication of twos complement numbers using N/21 X M/21 bit multipliers' [patent_app_type] => B1 [patent_app_number] => 09/260343 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3651 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347326.pdf [firstpage_image] =>[orig_patent_app_number] => 09260343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1432328 [patent_doc_number] => 06505220 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Method and apparatus for detecting a unique word' [patent_app_type] => B1 [patent_app_number] => 09/260780 [patent_app_country] => US [patent_app_date] => 1999-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5536 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505220.pdf [firstpage_image] =>[orig_patent_app_number] => 09260780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466574 [patent_doc_number] => 06351759 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Digital channelizer having efficient architecture for discrete fourier transformation and operation thereof' [patent_app_type] => B1 [patent_app_number] => 09/259623 [patent_app_country] => US [patent_app_date] => 1999-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 28 [patent_no_of_words] => 10666 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351759.pdf [firstpage_image] =>[orig_patent_app_number] => 09259623 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1471671 [patent_doc_number] => 06460063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-01 [patent_title] => 'Division circuit and graphic display processing apparatus' [patent_app_type] => B1 [patent_app_number] => 09/253951 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8713 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/460/06460063.pdf [firstpage_image] =>[orig_patent_app_number] => 09253951 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549310 [patent_doc_number] => 06374279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'System and method for increasing dual FIR filter efficiency' [patent_app_type] => B1 [patent_app_number] => 09/255393 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3106 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374279.pdf [firstpage_image] =>[orig_patent_app_number] => 09255393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4421476 [patent_doc_number] => 06272513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Multiplying device' [patent_app_type] => 1 [patent_app_number] => 9/253741 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16073 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272513.pdf [firstpage_image] =>[orig_patent_app_number] => 253741 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1434009 [patent_doc_number] => 06341299 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Modular arithmetic coprocessor enabling the performance of non-modular operations at high speed' [patent_app_type] => B1 [patent_app_number] => 09/253681 [patent_app_country] => US [patent_app_date] => 1999-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 11497 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341299.pdf [firstpage_image] =>[orig_patent_app_number] => 09253681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1405626 [patent_doc_number] => 06560625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Fast digital adder' [patent_app_type] => B1 [patent_app_number] => 09/252181 [patent_app_country] => US [patent_app_date] => 1999-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3705 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560625.pdf [firstpage_image] =>[orig_patent_app_number] => 09252181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4411609 [patent_doc_number] => 06298366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Reconfigurable multiply-accumulate hardware co-processor unit' [patent_app_type] => 1 [patent_app_number] => 9/244973 [patent_app_country] => US [patent_app_date] => 1999-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 9006 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298366.pdf [firstpage_image] =>[orig_patent_app_number] => 244973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466578 [patent_doc_number] => 06351760 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Division unit in a processor using a piece-wise quadratic approximation technique' [patent_app_type] => B1 [patent_app_number] => 09/240312 [patent_app_country] => US [patent_app_date] => 1999-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 8063 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351760.pdf [firstpage_image] =>[orig_patent_app_number] => 09240312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4373207 [patent_doc_number] => 06292817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Discrete cosine transformation circuit' [patent_app_type] => 1 [patent_app_number] => 9/239192 [patent_app_country] => US [patent_app_date] => 1999-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7270 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292817.pdf [firstpage_image] =>[orig_patent_app_number] => 239192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4123020 [patent_doc_number] => 06101518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus' [patent_app_type] => 1 [patent_app_number] => 9/236365 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 84 [patent_figures_cnt] => 155 [patent_no_of_words] => 33981 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101518.pdf [firstpage_image] =>[orig_patent_app_number] => 236365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4421423 [patent_doc_number] => 06272510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Arithmetic unit, correlation arithmetic unit and dynamic image compression apparatus' [patent_app_type] => 1 [patent_app_number] => 9/236225 [patent_app_country] => US [patent_app_date] => 1999-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 85 [patent_figures_cnt] => 155 [patent_no_of_words] => 34048 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272510.pdf [firstpage_image] =>[orig_patent_app_number] => 236225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4332747 [patent_doc_number] => 06332151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Time discrete filter' [patent_app_type] => 1 [patent_app_number] => 9/233842 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6450 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/332/06332151.pdf [firstpage_image] =>[orig_patent_app_number] => 233842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4332604 [patent_doc_number] => 06317772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Split remainder divider' [patent_app_type] => 1 [patent_app_number] => 9/234021 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317772.pdf [firstpage_image] =>[orig_patent_app_number] => 234021 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1481472 [patent_doc_number] => 06345285 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-05 [patent_title] => 'Logarithmic value calculation circuit' [patent_app_type] => B1 [patent_app_number] => 09/233661 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1273 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/345/06345285.pdf [firstpage_image] =>[orig_patent_app_number] => 09233661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1501319 [patent_doc_number] => 06405228 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Self-adjusting optimal delay time filter' [patent_app_type] => B1 [patent_app_number] => 09/231211 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2678 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/405/06405228.pdf [firstpage_image] =>[orig_patent_app_number] => 09231211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4170672 [patent_doc_number] => 06125378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Method and apparatus for generating families of code signals using multiscale shuffling' [patent_app_type] => 1 [patent_app_number] => 9/229614 [patent_app_country] => US [patent_app_date] => 1999-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3454 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125378.pdf [firstpage_image] =>[orig_patent_app_number] => 229614 [rel_patent_id] =>[rel_patent_doc_number] =>)