Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1553622 [patent_doc_number] => 06347324 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Ordering devices' [patent_app_type] => B1 [patent_app_number] => 09/228842 [patent_app_country] => US [patent_app_date] => 1999-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3604 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347324.pdf [firstpage_image] =>[orig_patent_app_number] => 09228842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/228842
Ordering devices Jan 11, 1999 Issued
Array ( [id] => 4056565 [patent_doc_number] => 05995994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Calculating A -sign(A) in a single instruction cycle' [patent_app_type] => 1 [patent_app_number] => 9/224187 [patent_app_country] => US [patent_app_date] => 1998-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4962 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995994.pdf [firstpage_image] =>[orig_patent_app_number] => 224187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/224187
Calculating A -sign(A) in a single instruction cycle Dec 30, 1998 Issued
Array ( [id] => 4332562 [patent_doc_number] => 06317769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Apparatus for calculating of Bc (mod n) with repeatedly shifting a holding value' [patent_app_type] => 1 [patent_app_number] => 9/219942 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 11434 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317769.pdf [firstpage_image] =>[orig_patent_app_number] => 219942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/219942
Apparatus for calculating of Bc (mod n) with repeatedly shifting a holding value Dec 22, 1998 Issued
Array ( [id] => 1474673 [patent_doc_number] => 06408319 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Electronic device for computing a fourier transform and corresponding control process' [patent_app_type] => B1 [patent_app_number] => 09/216563 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8794 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408319.pdf [firstpage_image] =>[orig_patent_app_number] => 09216563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/216563
Electronic device for computing a fourier transform and corresponding control process Dec 17, 1998 Issued
Array ( [id] => 4293712 [patent_doc_number] => 06324561 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Process and device for computing a fourier transform having a \"pipelined\" architecture' [patent_app_type] => 1 [patent_app_number] => 9/215082 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9298 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324561.pdf [firstpage_image] =>[orig_patent_app_number] => 215082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/215082
Process and device for computing a fourier transform having a "pipelined" architecture Dec 17, 1998 Issued
Array ( [id] => 1526310 [patent_doc_number] => 06353841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Reconfigurable processor devices' [patent_app_type] => B1 [patent_app_number] => 09/209542 [patent_app_country] => US [patent_app_date] => 1998-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 11907 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353841.pdf [firstpage_image] =>[orig_patent_app_number] => 09209542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209542
Reconfigurable processor devices Dec 10, 1998 Issued
Array ( [id] => 4387246 [patent_doc_number] => 06275840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Fast overflow detection in decoded bit-vector addition' [patent_app_type] => 1 [patent_app_number] => 9/209093 [patent_app_country] => US [patent_app_date] => 1998-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15724 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275840.pdf [firstpage_image] =>[orig_patent_app_number] => 209093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/209093
Fast overflow detection in decoded bit-vector addition Dec 9, 1998 Issued
Array ( [id] => 4421414 [patent_doc_number] => 06272509 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Filter device' [patent_app_type] => 1 [patent_app_number] => 9/208521 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5532 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272509.pdf [firstpage_image] =>[orig_patent_app_number] => 208521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208521
Filter device Dec 8, 1998 Issued
Array ( [id] => 4297764 [patent_doc_number] => 06282557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Low latency fused multiply-adder' [patent_app_type] => 1 [patent_app_number] => 9/207483 [patent_app_country] => US [patent_app_date] => 1998-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1996 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282557.pdf [firstpage_image] =>[orig_patent_app_number] => 207483 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207483
Low latency fused multiply-adder Dec 7, 1998 Issued
Array ( [id] => 975097 [patent_doc_number] => 06938064 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-08-30 [patent_title] => 'Method for computing fast Fourier transform and inverse fast Fourier transform' [patent_app_type] => utility [patent_app_number] => 09/581272 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 8932 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/938/06938064.pdf [firstpage_image] =>[orig_patent_app_number] => 09581272 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/581272
Method for computing fast Fourier transform and inverse fast Fourier transform Dec 6, 1998 Issued
Array ( [id] => 4304113 [patent_doc_number] => 06269387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method and apparatus for 3-stage 32-bit adder/subtractor' [patent_app_type] => 1 [patent_app_number] => 9/206463 [patent_app_country] => US [patent_app_date] => 1998-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 36 [patent_no_of_words] => 19788 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269387.pdf [firstpage_image] =>[orig_patent_app_number] => 206463 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/206463
Method and apparatus for 3-stage 32-bit adder/subtractor Dec 6, 1998 Issued
Array ( [id] => 4422850 [patent_doc_number] => 06311203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Multiplier, and fixed coefficient FIR digital filter having plural multipliers' [patent_app_type] => 1 [patent_app_number] => 9/203373 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4855 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311203.pdf [firstpage_image] =>[orig_patent_app_number] => 203373 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/203373
Multiplier, and fixed coefficient FIR digital filter having plural multipliers Dec 1, 1998 Issued
Array ( [id] => 4289498 [patent_doc_number] => 06308192 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Methods and apparatus for adaptive filters' [patent_app_type] => 1 [patent_app_number] => 9/201351 [patent_app_country] => US [patent_app_date] => 1998-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3344 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/308/06308192.pdf [firstpage_image] =>[orig_patent_app_number] => 201351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/201351
Methods and apparatus for adaptive filters Nov 29, 1998 Issued
Array ( [id] => 4422813 [patent_doc_number] => 06311199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Sign extension unit' [patent_app_type] => 1 [patent_app_number] => 9/199281 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3841 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311199.pdf [firstpage_image] =>[orig_patent_app_number] => 199281 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/199281
Sign extension unit Nov 24, 1998 Issued
Array ( [id] => 4024214 [patent_doc_number] => 06006246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Method of and apparatus for multiplying matrix data' [patent_app_type] => 1 [patent_app_number] => 9/197508 [patent_app_country] => US [patent_app_date] => 1998-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5140 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006246.pdf [firstpage_image] =>[orig_patent_app_number] => 197508 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/197508
Method of and apparatus for multiplying matrix data Nov 22, 1998 Issued
Array ( [id] => 4351019 [patent_doc_number] => 06314443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-06 [patent_title] => 'Double/saturate/add/saturate and double/saturate/subtract/saturate operations in a data processing system' [patent_app_type] => 1 [patent_app_number] => 9/196213 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3522 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/314/06314443.pdf [firstpage_image] =>[orig_patent_app_number] => 196213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196213
Double/saturate/add/saturate and double/saturate/subtract/saturate operations in a data processing system Nov 19, 1998 Issued
Array ( [id] => 4399370 [patent_doc_number] => 06304889 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Exponential optimization' [patent_app_type] => 1 [patent_app_number] => 9/195313 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3068 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304889.pdf [firstpage_image] =>[orig_patent_app_number] => 195313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195313
Exponential optimization Nov 17, 1998 Issued
Array ( [id] => 4421488 [patent_doc_number] => 06272514 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Method and apparatus for interruption of carry propagation on partition boundaries' [patent_app_type] => 1 [patent_app_number] => 9/195751 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 38 [patent_no_of_words] => 36404 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272514.pdf [firstpage_image] =>[orig_patent_app_number] => 195751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195751
Method and apparatus for interruption of carry propagation on partition boundaries Nov 17, 1998 Issued
Array ( [id] => 4423788 [patent_doc_number] => 06301597 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method and apparatus for saturation in an N-NARY adder/subtractor' [patent_app_type] => 1 [patent_app_number] => 9/195024 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 38 [patent_no_of_words] => 36301 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301597.pdf [firstpage_image] =>[orig_patent_app_number] => 195024 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195024
Method and apparatus for saturation in an N-NARY adder/subtractor Nov 17, 1998 Issued
Array ( [id] => 4423818 [patent_doc_number] => 06301600 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Method and apparatus for dynamic partitionable saturating adder/subtractor' [patent_app_type] => 1 [patent_app_number] => 9/195752 [patent_app_country] => US [patent_app_date] => 1998-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 38 [patent_no_of_words] => 36355 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301600.pdf [firstpage_image] =>[orig_patent_app_number] => 195752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195752
Method and apparatus for dynamic partitionable saturating adder/subtractor Nov 17, 1998 Issued
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