Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
09/117226 ADAPTIVE FILTERS AND EQUALISERS Nov 15, 1998 Abandoned
Array ( [id] => 4390743 [patent_doc_number] => 06289367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Digital signal processing circuits, systems, and method implementing approximations for logarithm and inverse logarithm' [patent_app_type] => 1 [patent_app_number] => 9/192981 [patent_app_country] => US [patent_app_date] => 1998-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 12781 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289367.pdf [firstpage_image] =>[orig_patent_app_number] => 192981 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192981
Digital signal processing circuits, systems, and method implementing approximations for logarithm and inverse logarithm Nov 15, 1998 Issued
Array ( [id] => 4122992 [patent_doc_number] => 06101516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Normalization shift prediction independent of operand subtraction' [patent_app_type] => 1 [patent_app_number] => 9/191143 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 15837 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/101/06101516.pdf [firstpage_image] =>[orig_patent_app_number] => 191143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191143
Normalization shift prediction independent of operand subtraction Nov 12, 1998 Issued
Array ( [id] => 4398625 [patent_doc_number] => 06295544 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Calculator for determining sizes and spans of wooden structural supports' [patent_app_type] => 1 [patent_app_number] => 9/191673 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4976 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295544.pdf [firstpage_image] =>[orig_patent_app_number] => 191673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/191673
Calculator for determining sizes and spans of wooden structural supports Nov 12, 1998 Issued
Array ( [id] => 1466565 [patent_doc_number] => 06351757 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Method for conserving memory storage during an interpolation operation' [patent_app_type] => B1 [patent_app_number] => 09/192044 [patent_app_country] => US [patent_app_date] => 1998-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351757.pdf [firstpage_image] =>[orig_patent_app_number] => 09192044 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192044
Method for conserving memory storage during an interpolation operation Nov 12, 1998 Issued
Array ( [id] => 4424339 [patent_doc_number] => 06230178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method for the production of an error correction parameter associated with the implementation of a modular operation according to the Montgomery method' [patent_app_type] => 1 [patent_app_number] => 9/190734 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5150 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230178.pdf [firstpage_image] =>[orig_patent_app_number] => 190734 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/190734
Method for the production of an error correction parameter associated with the implementation of a modular operation according to the Montgomery method Nov 11, 1998 Issued
Array ( [id] => 4398639 [patent_doc_number] => 06295545 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Reduction of execution times for convolution operations' [patent_app_type] => 1 [patent_app_number] => 9/192394 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3237 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295545.pdf [firstpage_image] =>[orig_patent_app_number] => 192394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/192394
Reduction of execution times for convolution operations Nov 11, 1998 Issued
Array ( [id] => 4387260 [patent_doc_number] => 06275841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => '1-of-4 multiplier' [patent_app_type] => 1 [patent_app_number] => 9/186843 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 10093 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275841.pdf [firstpage_image] =>[orig_patent_app_number] => 186843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186843
1-of-4 multiplier Nov 4, 1998 Issued
Array ( [id] => 4365277 [patent_doc_number] => 06286021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Apparatus and method for a reduced complexity tap leakage unit in a fast adaptive filter circuit' [patent_app_type] => 1 [patent_app_number] => 9/176684 [patent_app_country] => US [patent_app_date] => 1998-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2320 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286021.pdf [firstpage_image] =>[orig_patent_app_number] => 176684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/176684
Apparatus and method for a reduced complexity tap leakage unit in a fast adaptive filter circuit Oct 20, 1998 Issued
Array ( [id] => 4293686 [patent_doc_number] => 06324559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Odd-transform fast convolution' [patent_app_type] => 1 [patent_app_number] => 9/173803 [patent_app_country] => US [patent_app_date] => 1998-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 7320 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324559.pdf [firstpage_image] =>[orig_patent_app_number] => 173803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/173803
Odd-transform fast convolution Oct 15, 1998 Issued
Array ( [id] => 4279845 [patent_doc_number] => 06260055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Data split parallel shifter and parallel adder/subtractor' [patent_app_type] => 1 [patent_app_number] => 9/172772 [patent_app_country] => US [patent_app_date] => 1998-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 11196 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260055.pdf [firstpage_image] =>[orig_patent_app_number] => 172772 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172772
Data split parallel shifter and parallel adder/subtractor Oct 14, 1998 Issued
Array ( [id] => 4304100 [patent_doc_number] => 06269386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => '3X adder' [patent_app_type] => 1 [patent_app_number] => 9/172933 [patent_app_country] => US [patent_app_date] => 1998-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3203 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269386.pdf [firstpage_image] =>[orig_patent_app_number] => 172933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/172933
3X adder Oct 13, 1998 Issued
Array ( [id] => 4421448 [patent_doc_number] => 06272512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Data manipulation instruction for enhancing value and efficiency of complex arithmetic' [patent_app_type] => 1 [patent_app_number] => 9/170473 [patent_app_country] => US [patent_app_date] => 1998-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272512.pdf [firstpage_image] =>[orig_patent_app_number] => 170473 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/170473
Data manipulation instruction for enhancing value and efficiency of complex arithmetic Oct 11, 1998 Issued
Array ( [id] => 4309115 [patent_doc_number] => 06212539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Methods and apparatus for handling and storing bi-endian words in a floating-point processor' [patent_app_type] => 1 [patent_app_number] => 9/169483 [patent_app_country] => US [patent_app_date] => 1998-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8382 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212539.pdf [firstpage_image] =>[orig_patent_app_number] => 169483 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169483
Methods and apparatus for handling and storing bi-endian words in a floating-point processor Oct 9, 1998 Issued
Array ( [id] => 4278774 [patent_doc_number] => 06205458 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith' [patent_app_type] => 1 [patent_app_number] => 9/158947 [patent_app_country] => US [patent_app_date] => 1998-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 6620 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205458.pdf [firstpage_image] =>[orig_patent_app_number] => 158947 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158947
Adder and multiplier circuits employing logic gates having discrete, weighted inputs and methods of performing combinatorial operations therewith Sep 20, 1998 Issued
Array ( [id] => 4380314 [patent_doc_number] => 06256655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Method and system for performing floating point operations in unnormalized format using a floating point accumulator' [patent_app_type] => 1 [patent_app_number] => 9/153153 [patent_app_country] => US [patent_app_date] => 1998-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8179 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/256/06256655.pdf [firstpage_image] =>[orig_patent_app_number] => 153153 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/153153
Method and system for performing floating point operations in unnormalized format using a floating point accumulator Sep 13, 1998 Issued
Array ( [id] => 4375362 [patent_doc_number] => 06219682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Vector normalizing apparatus' [patent_app_type] => 1 [patent_app_number] => 9/150008 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 11069 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219682.pdf [firstpage_image] =>[orig_patent_app_number] => 150008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150008
Vector normalizing apparatus Sep 8, 1998 Issued
Array ( [id] => 4403277 [patent_doc_number] => 06263357 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Parallel multiplier' [patent_app_type] => 1 [patent_app_number] => 9/150174 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2611 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/263/06263357.pdf [firstpage_image] =>[orig_patent_app_number] => 150174 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150174
Parallel multiplier Sep 8, 1998 Issued
Array ( [id] => 4315409 [patent_doc_number] => 06199084 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Methods and apparatus for implementing weighted median filters' [patent_app_type] => 1 [patent_app_number] => 9/149679 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6840 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199084.pdf [firstpage_image] =>[orig_patent_app_number] => 149679 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149679
Methods and apparatus for implementing weighted median filters Sep 8, 1998 Issued
Array ( [id] => 4427237 [patent_doc_number] => 06226660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Efficient method of implementing random number generators' [patent_app_type] => 1 [patent_app_number] => 9/148899 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1996 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226660.pdf [firstpage_image] =>[orig_patent_app_number] => 148899 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/148899
Efficient method of implementing random number generators Sep 7, 1998 Issued
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