Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4345364 [patent_doc_number] => 06330581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Apparatus and a method for address generation' [patent_app_type] => 1 [patent_app_number] => 9/149881 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2348 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/330/06330581.pdf [firstpage_image] =>[orig_patent_app_number] => 149881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149881
Apparatus and a method for address generation Sep 7, 1998 Issued
Array ( [id] => 4424162 [patent_doc_number] => 06266685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Hand-held data collection system with stylus input' [patent_app_type] => 1 [patent_app_number] => 9/149414 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 30 [patent_no_of_words] => 16049 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266685.pdf [firstpage_image] =>[orig_patent_app_number] => 149414 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149414
Hand-held data collection system with stylus input Sep 7, 1998 Issued
Array ( [id] => 4375403 [patent_doc_number] => 06219685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method to detect IEEE overflow and underflow conditions' [patent_app_type] => 1 [patent_app_number] => 9/148173 [patent_app_country] => US [patent_app_date] => 1998-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3816 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219685.pdf [firstpage_image] =>[orig_patent_app_number] => 148173 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/148173
Method to detect IEEE overflow and underflow conditions Sep 3, 1998 Issued
Array ( [id] => 6818956 [patent_doc_number] => 20030069914 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'CARRY LOOKAHEAD ADDER HAVING A REDUCED FANOUT ARCHITECTURE' [patent_app_type] => new [patent_app_number] => 09/146693 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6823 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20030069914.pdf [firstpage_image] =>[orig_patent_app_number] => 09146693 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146693
CARRY LOOKAHEAD ADDER HAVING A REDUCED FANOUT ARCHITECTURE Sep 2, 1998 Abandoned
Array ( [id] => 4332577 [patent_doc_number] => 06317770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'High speed digital signal processor' [patent_app_type] => 1 [patent_app_number] => 9/144284 [patent_app_country] => US [patent_app_date] => 1998-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 7413 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/317/06317770.pdf [firstpage_image] =>[orig_patent_app_number] => 144284 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/144284
High speed digital signal processor Aug 30, 1998 Issued
Array ( [id] => 4151621 [patent_doc_number] => 06148314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Round increment in an adder circuit' [patent_app_type] => 1 [patent_app_number] => 9/143614 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2885 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148314.pdf [firstpage_image] =>[orig_patent_app_number] => 143614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143614
Round increment in an adder circuit Aug 27, 1998 Issued
Array ( [id] => 4272799 [patent_doc_number] => 06209017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'High speed digital signal processor' [patent_app_type] => 1 [patent_app_number] => 9/143351 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9770 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209017.pdf [firstpage_image] =>[orig_patent_app_number] => 143351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143351
High speed digital signal processor Aug 27, 1998 Issued
Array ( [id] => 4267960 [patent_doc_number] => 06138135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Propagating NaNs during high precision calculations using lesser precision hardware' [patent_app_type] => 1 [patent_app_number] => 9/141246 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6025 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138135.pdf [firstpage_image] =>[orig_patent_app_number] => 141246 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/141246
Propagating NaNs during high precision calculations using lesser precision hardware Aug 26, 1998 Issued
Array ( [id] => 4316516 [patent_doc_number] => 06182105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Multiple-operand addition with intermediate saturation' [patent_app_type] => 1 [patent_app_number] => 9/140959 [patent_app_country] => US [patent_app_date] => 1998-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2238 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182105.pdf [firstpage_image] =>[orig_patent_app_number] => 140959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140959
Multiple-operand addition with intermediate saturation Aug 26, 1998 Issued
Array ( [id] => 4421745 [patent_doc_number] => 06173304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Joint optimization of modified-booth encoder and partial product generator' [patent_app_type] => 1 [patent_app_number] => 9/137390 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3269 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173304.pdf [firstpage_image] =>[orig_patent_app_number] => 137390 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137390
Joint optimization of modified-booth encoder and partial product generator Aug 19, 1998 Issued
Array ( [id] => 4178117 [patent_doc_number] => 06115729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Floating point multiply-accumulate unit' [patent_app_type] => 1 [patent_app_number] => 9/136843 [patent_app_country] => US [patent_app_date] => 1998-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3113 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115729.pdf [firstpage_image] =>[orig_patent_app_number] => 136843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136843
Floating point multiply-accumulate unit Aug 19, 1998 Issued
Array ( [id] => 4316783 [patent_doc_number] => 06185594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Versatile signal generator' [patent_app_type] => 1 [patent_app_number] => 9/136877 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6252 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185594.pdf [firstpage_image] =>[orig_patent_app_number] => 136877 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136877
Versatile signal generator Aug 18, 1998 Issued
Array ( [id] => 4269302 [patent_doc_number] => 06223198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method and apparatus for multi-function arithmetic' [patent_app_type] => 1 [patent_app_number] => 9/134171 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 41 [patent_no_of_words] => 24437 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223198.pdf [firstpage_image] =>[orig_patent_app_number] => 134171 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134171
Method and apparatus for multi-function arithmetic Aug 13, 1998 Issued
Array ( [id] => 4151665 [patent_doc_number] => 06148317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Method and apparatus for compressing signals in a fixed point format without introducing a bias' [patent_app_type] => 1 [patent_app_number] => 9/134248 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3509 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148317.pdf [firstpage_image] =>[orig_patent_app_number] => 134248 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134248
Method and apparatus for compressing signals in a fixed point format without introducing a bias Aug 13, 1998 Issued
Array ( [id] => 4421707 [patent_doc_number] => 06173300 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method and circuit for determining leading or trailing zero count' [patent_app_type] => 1 [patent_app_number] => 9/132524 [patent_app_country] => US [patent_app_date] => 1998-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 5 [patent_no_of_words] => 4824 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173300.pdf [firstpage_image] =>[orig_patent_app_number] => 132524 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/132524
Method and circuit for determining leading or trailing zero count Aug 10, 1998 Issued
Array ( [id] => 4421715 [patent_doc_number] => 06173301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method of generating signal amplitude responsive to desired function, and converter' [patent_app_type] => 1 [patent_app_number] => 9/117976 [patent_app_country] => US [patent_app_date] => 1998-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4204 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173301.pdf [firstpage_image] =>[orig_patent_app_number] => 117976 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/117976
Method of generating signal amplitude responsive to desired function, and converter Aug 10, 1998 Issued
Array ( [id] => 4372897 [patent_doc_number] => 06202074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Multiplierless digital filtering' [patent_app_type] => 1 [patent_app_number] => 9/131336 [patent_app_country] => US [patent_app_date] => 1998-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3115 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/202/06202074.pdf [firstpage_image] =>[orig_patent_app_number] => 131336 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/131336
Multiplierless digital filtering Aug 6, 1998 Issued
Array ( [id] => 4176549 [patent_doc_number] => 06108679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Discontinuous signal interpolation circuit' [patent_app_type] => 1 [patent_app_number] => 9/129614 [patent_app_country] => US [patent_app_date] => 1998-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 2580 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108679.pdf [firstpage_image] =>[orig_patent_app_number] => 129614 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/129614
Discontinuous signal interpolation circuit Aug 4, 1998 Issued
Array ( [id] => 4373364 [patent_doc_number] => 06175847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Shifting for parallel normalization and rounding technique for floating point arithmetic operations' [patent_app_type] => 1 [patent_app_number] => 9/120814 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9345 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175847.pdf [firstpage_image] =>[orig_patent_app_number] => 120814 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120814
Shifting for parallel normalization and rounding technique for floating point arithmetic operations Jul 21, 1998 Issued
Array ( [id] => 4421700 [patent_doc_number] => 06173299 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method and apparatus for selecting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations' [patent_app_type] => 1 [patent_app_number] => 9/120771 [patent_app_country] => US [patent_app_date] => 1998-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9315 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173299.pdf [firstpage_image] =>[orig_patent_app_number] => 120771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/120771
Method and apparatus for selecting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations Jul 21, 1998 Issued
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