Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4373391 [patent_doc_number] => 06175849 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'System for digital filtering in a fixed number of clock cycles' [patent_app_type] => 1 [patent_app_number] => 9/021582 [patent_app_country] => US [patent_app_date] => 1998-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 37 [patent_no_of_words] => 20357 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/175/06175849.pdf [firstpage_image] =>[orig_patent_app_number] => 021582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/021582
System for digital filtering in a fixed number of clock cycles Feb 9, 1998 Issued
09/019146 VERSATILE SIGNAL GENERATOR Feb 4, 1998 Abandoned
Array ( [id] => 4411539 [patent_doc_number] => 06298361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Signal encoding and decoding system' [patent_app_type] => 1 [patent_app_number] => 9/013492 [patent_app_country] => US [patent_app_date] => 1998-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 55 [patent_no_of_words] => 14498 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 21 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298361.pdf [firstpage_image] =>[orig_patent_app_number] => 013492 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/013492
Signal encoding and decoding system Jan 25, 1998 Issued
Array ( [id] => 4223069 [patent_doc_number] => 06078940 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Microprocessor with an instruction for multiply and left shift with saturate' [patent_app_type] => 1 [patent_app_number] => 9/012380 [patent_app_country] => US [patent_app_date] => 1998-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 3933 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078940.pdf [firstpage_image] =>[orig_patent_app_number] => 012380 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/012380
Microprocessor with an instruction for multiply and left shift with saturate Jan 22, 1998 Issued
Array ( [id] => 4193737 [patent_doc_number] => 06085210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'High-speed modular exponentiator and multiplier' [patent_app_type] => 1 [patent_app_number] => 9/010897 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7310 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085210.pdf [firstpage_image] =>[orig_patent_app_number] => 010897 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010897
High-speed modular exponentiator and multiplier Jan 21, 1998 Issued
Array ( [id] => 3966167 [patent_doc_number] => 05983252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Pseudo-random number generator capable of efficiently exploiting processors having instruction-level parallelism and the use thereof for encryption' [patent_app_type] => 1 [patent_app_number] => 9/007944 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 7873 [patent_no_of_claims] => 86 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983252.pdf [firstpage_image] =>[orig_patent_app_number] => 007944 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/007944
Pseudo-random number generator capable of efficiently exploiting processors having instruction-level parallelism and the use thereof for encryption Jan 15, 1998 Issued
Array ( [id] => 4251735 [patent_doc_number] => 06076096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Binary rate multiplier' [patent_app_type] => 1 [patent_app_number] => 9/006212 [patent_app_country] => US [patent_app_date] => 1998-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3546 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076096.pdf [firstpage_image] =>[orig_patent_app_number] => 006212 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/006212
Binary rate multiplier Jan 12, 1998 Issued
Array ( [id] => 4121166 [patent_doc_number] => 06052704 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Exponentiation circuit and inverter based on power-sum circuit for finite field GF(2.sup.m)' [patent_app_type] => 1 [patent_app_number] => 9/005882 [patent_app_country] => US [patent_app_date] => 1998-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9197 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052704.pdf [firstpage_image] =>[orig_patent_app_number] => 005882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/005882
Exponentiation circuit and inverter based on power-sum circuit for finite field GF(2.sup.m) Jan 11, 1998 Issued
Array ( [id] => 1459800 [patent_doc_number] => 06463453 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Low power pipelined multiply/accumulator with modified booth\'s recoder' [patent_app_type] => B1 [patent_app_number] => 09/006054 [patent_app_country] => US [patent_app_date] => 1998-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3548 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463453.pdf [firstpage_image] =>[orig_patent_app_number] => 09006054 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/006054
Low power pipelined multiply/accumulator with modified booth's recoder Jan 11, 1998 Issued
Array ( [id] => 4254045 [patent_doc_number] => 06119140 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Two-dimensional inverse discrete cosine transform circuit and microprocessor realizing the same and method of implementing 8.times.8 two-dimensional inverse discrete cosine transform' [patent_app_type] => 1 [patent_app_number] => 9/004330 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4705 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119140.pdf [firstpage_image] =>[orig_patent_app_number] => 004330 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004330
Two-dimensional inverse discrete cosine transform circuit and microprocessor realizing the same and method of implementing 8.times.8 two-dimensional inverse discrete cosine transform Jan 7, 1998 Issued
Array ( [id] => 4198072 [patent_doc_number] => 06038579 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Digital signal processing apparatus for performing wavelet transform' [patent_app_type] => 1 [patent_app_number] => 9/002916 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 22 [patent_no_of_words] => 7148 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038579.pdf [firstpage_image] =>[orig_patent_app_number] => 002916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002916
Digital signal processing apparatus for performing wavelet transform Jan 4, 1998 Issued
Array ( [id] => 4315441 [patent_doc_number] => 06199086 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Circuit and method for decompressing compressed elliptic curve points' [patent_app_type] => 1 [patent_app_number] => 8/997959 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3526 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/199/06199086.pdf [firstpage_image] =>[orig_patent_app_number] => 997959 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997959
Circuit and method for decompressing compressed elliptic curve points Dec 23, 1997 Issued
Array ( [id] => 4150778 [patent_doc_number] => 06035310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method and circuit for performing a shift arithmetic right operation' [patent_app_type] => 1 [patent_app_number] => 8/995119 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3543 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035310.pdf [firstpage_image] =>[orig_patent_app_number] => 995119 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995119
Method and circuit for performing a shift arithmetic right operation Dec 18, 1997 Issued
Array ( [id] => 4024185 [patent_doc_number] => 06006244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Circuit for shifting or rotating operands of multiple size' [patent_app_type] => 1 [patent_app_number] => 8/994816 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6075 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/006/06006244.pdf [firstpage_image] =>[orig_patent_app_number] => 994816 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994816
Circuit for shifting or rotating operands of multiple size Dec 18, 1997 Issued
Array ( [id] => 3968423 [patent_doc_number] => 05948049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Normalization circuitry' [patent_app_type] => 1 [patent_app_number] => 8/986300 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 14663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 670 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948049.pdf [firstpage_image] =>[orig_patent_app_number] => 986300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/986300
Normalization circuitry Dec 4, 1997 Issued
Array ( [id] => 3996441 [patent_doc_number] => 05961577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Random binary number generator' [patent_app_type] => 1 [patent_app_number] => 8/985937 [patent_app_country] => US [patent_app_date] => 1997-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3328 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/961/05961577.pdf [firstpage_image] =>[orig_patent_app_number] => 985937 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/985937
Random binary number generator Dec 4, 1997 Issued
Array ( [id] => 825348 [patent_doc_number] => 07406492 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-07-29 [patent_title] => 'Digital filter combination for interpolation' [patent_app_type] => utility [patent_app_number] => 08/984735 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3522 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/406/07406492.pdf [firstpage_image] =>[orig_patent_app_number] => 08984735 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984735
Digital filter combination for interpolation Dec 3, 1997 Issued
Array ( [id] => 3931815 [patent_doc_number] => 06003052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Portable information instrument having a display cover protecting a display screen' [patent_app_type] => 1 [patent_app_number] => 8/984948 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6325 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003052.pdf [firstpage_image] =>[orig_patent_app_number] => 984948 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984948
Portable information instrument having a display cover protecting a display screen Dec 3, 1997 Issued
Array ( [id] => 3939526 [patent_doc_number] => 05954788 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Apparatus for performing modular multiplication' [patent_app_type] => 1 [patent_app_number] => 8/984505 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1961 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/954/05954788.pdf [firstpage_image] =>[orig_patent_app_number] => 984505 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984505
Apparatus for performing modular multiplication Dec 2, 1997 Issued
Array ( [id] => 4170714 [patent_doc_number] => 06125381 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Recursively partitioned carry select adder' [patent_app_type] => 1 [patent_app_number] => 8/984572 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1751 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 372 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125381.pdf [firstpage_image] =>[orig_patent_app_number] => 984572 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984572
Recursively partitioned carry select adder Dec 2, 1997 Issued
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