Richard L Schilling

Array ( [id] => 3966248 [patent_doc_number] => 05983258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Apparatus and method for summing 1-bit signals' [patent_app_type] => 1 [patent_app_number] => 8/979469 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3938 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983258.pdf [firstpage_image] =>[orig_patent_app_number] => 979469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4365264 [patent_doc_number] => 06286020 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Signal processor delta-sigma modulator stage' [patent_app_type] => 1 [patent_app_number] => 8/979761 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3589 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286020.pdf [firstpage_image] =>[orig_patent_app_number] => 979761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1580090 [patent_doc_number] => 06470371 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Parallel multiplier' [patent_app_type] => B1 [patent_app_number] => 08/976596 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 5801 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470371.pdf [firstpage_image] =>[orig_patent_app_number] => 08976596 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3944617 [patent_doc_number] => 05935200 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Exponential functional relationship generator method and system for implementation in digital logic' [patent_app_type] => 1 [patent_app_number] => 8/975273 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5249 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/935/05935200.pdf [firstpage_image] =>[orig_patent_app_number] => 975273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3931824 [patent_doc_number] => 06003053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Pulse signal generation circuit and pulse signal generation method' [patent_app_type] => 1 [patent_app_number] => 8/971846 [patent_app_country] => US [patent_app_date] => 1997-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 6380 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003053.pdf [firstpage_image] =>[orig_patent_app_number] => 971846 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4063154 [patent_doc_number] => 05964827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'High-speed binary adder' [patent_app_type] => 1 [patent_app_number] => 8/971653 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2768 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/964/05964827.pdf [firstpage_image] =>[orig_patent_app_number] => 971653 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1456470 [patent_doc_number] => 06457032 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Efficient flexible digital filtering' [patent_app_type] => B1 [patent_app_number] => 08/971241 [patent_app_country] => US [patent_app_date] => 1997-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 8581 [patent_no_of_claims] => 108 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457032.pdf [firstpage_image] =>[orig_patent_app_number] => 08971241 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3972452 [patent_doc_number] => 05978825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Zero detection circuitry and methods' [patent_app_type] => 1 [patent_app_number] => 8/970796 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 10111 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978825.pdf [firstpage_image] =>[orig_patent_app_number] => 970796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4020765 [patent_doc_number] => 05987490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Mac processor with efficient Viterbi ACS operation and automatic traceback store' [patent_app_type] => 1 [patent_app_number] => 8/970921 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5101 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987490.pdf [firstpage_image] =>[orig_patent_app_number] => 970921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3914839 [patent_doc_number] => 05944772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Combined adder and logic unit' [patent_app_type] => 1 [patent_app_number] => 8/970076 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2985 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944772.pdf [firstpage_image] =>[orig_patent_app_number] => 970076 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3969472 [patent_doc_number] => 05991785 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Determining an extremum value and its index in an array using a dual-accumulation processor' [patent_app_type] => 1 [patent_app_number] => 8/969252 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2864 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991785.pdf [firstpage_image] =>[orig_patent_app_number] => 969252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3922872 [patent_doc_number] => 05928319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Combined binary/decimal adder unit' [patent_app_type] => 1 [patent_app_number] => 8/969244 [patent_app_country] => US [patent_app_date] => 1997-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3587 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 301 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928319.pdf [firstpage_image] =>[orig_patent_app_number] => 969244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3896166 [patent_doc_number] => 05894427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Technique for concurrent detection of bit patterns' [patent_app_type] => 1 [patent_app_number] => 8/968565 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4883 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894427.pdf [firstpage_image] =>[orig_patent_app_number] => 968565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4041837 [patent_doc_number] => 05931893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Efficient correlation over a sliding window' [patent_app_type] => 1 [patent_app_number] => 8/967444 [patent_app_country] => US [patent_app_date] => 1997-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6222 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931893.pdf [firstpage_image] =>[orig_patent_app_number] => 967444 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4125974 [patent_doc_number] => 06058405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'SIMD computation of rank based filters for M.times.N grids' [patent_app_type] => 1 [patent_app_number] => 8/965686 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6639 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058405.pdf [firstpage_image] =>[orig_patent_app_number] => 965686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4025528 [patent_doc_number] => 05941937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Layout structure for barrel shifter with decode circuit' [patent_app_type] => 1 [patent_app_number] => 8/959374 [patent_app_country] => US [patent_app_date] => 1997-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4081 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941937.pdf [firstpage_image] =>[orig_patent_app_number] => 959374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4102997 [patent_doc_number] => 06026418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Frequency measurement method and associated apparatus' [patent_app_type] => 1 [patent_app_number] => 8/957915 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 12605 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026418.pdf [firstpage_image] =>[orig_patent_app_number] => 957915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4077238 [patent_doc_number] => 05867407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Normalization shift prediction independent of operand substraction' [patent_app_type] => 1 [patent_app_number] => 8/955087 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 15676 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867407.pdf [firstpage_image] =>[orig_patent_app_number] => 955087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4025591 [patent_doc_number] => 05941941 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-24 [patent_title] => 'Bit width controlling method' [patent_app_type] => 1 [patent_app_number] => 8/943141 [patent_app_country] => US [patent_app_date] => 1997-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3454 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/941/05941941.pdf [firstpage_image] =>[orig_patent_app_number] => 943141 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4159457 [patent_doc_number] => 06061702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Random number generator' [patent_app_type] => 1 [patent_app_number] => 8/939804 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3783 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/061/06061702.pdf [firstpage_image] =>[orig_patent_app_number] => 939804 [rel_patent_id] =>[rel_patent_doc_number] =>)