Search

Richard L Schilling

Examiner (ID: 9849)

Most Active Art Unit
1506
Art Unit(s)
1506, 1752, 1302, 1795, 1715, 1113
Total Applications
3259
Issued Applications
2786
Pending Applications
25
Abandoned Applications
448

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3914875 [patent_doc_number] => 05944774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Methods apparatus and computer program products for accumulating logarithmic values' [patent_app_type] => 1 [patent_app_number] => 8/938410 [patent_app_country] => US [patent_app_date] => 1997-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 14696 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/944/05944774.pdf [firstpage_image] =>[orig_patent_app_number] => 938410 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/938410
Methods apparatus and computer program products for accumulating logarithmic values Sep 25, 1997 Issued
Array ( [id] => 1431776 [patent_doc_number] => 06516334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Circuit arrangement with combinatorial blocks arranged between registers' [patent_app_type] => B1 [patent_app_number] => 08/933880 [patent_app_country] => US [patent_app_date] => 1997-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1295 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516334.pdf [firstpage_image] =>[orig_patent_app_number] => 08933880 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/933880
Circuit arrangement with combinatorial blocks arranged between registers Sep 18, 1997 Issued
Array ( [id] => 4041809 [patent_doc_number] => 05931891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Digital frequency synthesizer' [patent_app_type] => 1 [patent_app_number] => 8/932769 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3480 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/931/05931891.pdf [firstpage_image] =>[orig_patent_app_number] => 932769 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932769
Digital frequency synthesizer Sep 17, 1997 Issued
Array ( [id] => 3972391 [patent_doc_number] => 05978821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Smart modular electronic machine' [patent_app_type] => 1 [patent_app_number] => 8/932907 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5392 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978821.pdf [firstpage_image] =>[orig_patent_app_number] => 932907 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/932907
Smart modular electronic machine Sep 16, 1997 Issued
Array ( [id] => 3993718 [patent_doc_number] => 05910908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Fir filter for programmable decimation' [patent_app_type] => 1 [patent_app_number] => 8/931408 [patent_app_country] => US [patent_app_date] => 1997-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3227 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910908.pdf [firstpage_image] =>[orig_patent_app_number] => 931408 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/931408
Fir filter for programmable decimation Sep 15, 1997 Issued
Array ( [id] => 4004756 [patent_doc_number] => 05892699 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method and apparatus for optimizing dependent operand flow within a multiplier using recoding logic' [patent_app_type] => 1 [patent_app_number] => 8/931859 [patent_app_country] => US [patent_app_date] => 1997-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4574 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892699.pdf [firstpage_image] =>[orig_patent_app_number] => 931859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/931859
Method and apparatus for optimizing dependent operand flow within a multiplier using recoding logic Sep 15, 1997 Issued
Array ( [id] => 3915429 [patent_doc_number] => 05951629 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Method and apparatus for log conversion with scaling' [patent_app_type] => 1 [patent_app_number] => 8/929607 [patent_app_country] => US [patent_app_date] => 1997-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/951/05951629.pdf [firstpage_image] =>[orig_patent_app_number] => 929607 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/929607
Method and apparatus for log conversion with scaling Sep 14, 1997 Issued
Array ( [id] => 3922812 [patent_doc_number] => 05928315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Apparatus and method for calculating B.sup.c (mod n)' [patent_app_type] => 1 [patent_app_number] => 8/928538 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9544 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/928/05928315.pdf [firstpage_image] =>[orig_patent_app_number] => 928538 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/928538
Apparatus and method for calculating B.sup.c (mod n) Sep 11, 1997 Issued
Array ( [id] => 3915026 [patent_doc_number] => 05898604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Digital Signal Processor employing a random-access memory and method for performing multiplication' [patent_app_type] => 1 [patent_app_number] => 8/928575 [patent_app_country] => US [patent_app_date] => 1997-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2357 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898604.pdf [firstpage_image] =>[orig_patent_app_number] => 928575 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/928575
Digital Signal Processor employing a random-access memory and method for performing multiplication Sep 11, 1997 Issued
Array ( [id] => 3931892 [patent_doc_number] => 06003058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Apparatus and methods for performing arithimetic operations on vectors and/or matrices' [patent_app_type] => 1 [patent_app_number] => 8/924288 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5533 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003058.pdf [firstpage_image] =>[orig_patent_app_number] => 924288 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/924288
Apparatus and methods for performing arithimetic operations on vectors and/or matrices Sep 4, 1997 Issued
Array ( [id] => 1336423 [patent_doc_number] => 06604120 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-05 [patent_title] => 'Multiplier power saving design' [patent_app_type] => B1 [patent_app_number] => 08/923133 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4649 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/604/06604120.pdf [firstpage_image] =>[orig_patent_app_number] => 08923133 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/923133
Multiplier power saving design Sep 3, 1997 Issued
Array ( [id] => 4279562 [patent_doc_number] => 06183122 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Multiplier sign extension' [patent_app_type] => 1 [patent_app_number] => 8/923132 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4762 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/183/06183122.pdf [firstpage_image] =>[orig_patent_app_number] => 923132 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/923132
Multiplier sign extension Sep 3, 1997 Issued
Array ( [id] => 3853310 [patent_doc_number] => 05847981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Multiply and accumulate circuit' [patent_app_type] => 1 [patent_app_number] => 8/923329 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847981.pdf [firstpage_image] =>[orig_patent_app_number] => 923329 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/923329
Multiply and accumulate circuit Sep 3, 1997 Issued
Array ( [id] => 4193793 [patent_doc_number] => 06085214 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Digital multiplier with multiplier encoding involving 3X term' [patent_app_type] => 1 [patent_app_number] => 8/923693 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 4682 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085214.pdf [firstpage_image] =>[orig_patent_app_number] => 923693 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/923693
Digital multiplier with multiplier encoding involving 3X term Sep 3, 1997 Issued
Array ( [id] => 4120943 [patent_doc_number] => 06023719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Signal processor and method for fast Fourier transformation' [patent_app_type] => 1 [patent_app_number] => 8/923687 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4272 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023719.pdf [firstpage_image] =>[orig_patent_app_number] => 923687 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/923687
Signal processor and method for fast Fourier transformation Sep 3, 1997 Issued
Array ( [id] => 4036896 [patent_doc_number] => 05883825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-16 [patent_title] => 'Reduction of partial product arrays using pre-propagate set-up' [patent_app_type] => 1 [patent_app_number] => 8/922735 [patent_app_country] => US [patent_app_date] => 1997-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3778 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/883/05883825.pdf [firstpage_image] =>[orig_patent_app_number] => 922735 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/922735
Reduction of partial product arrays using pre-propagate set-up Sep 2, 1997 Issued
Array ( [id] => 4038226 [patent_doc_number] => 05903479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Method and system for executing denormalized numbers' [patent_app_type] => 1 [patent_app_number] => 8/922191 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3057 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903479.pdf [firstpage_image] =>[orig_patent_app_number] => 922191 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/922191
Method and system for executing denormalized numbers Sep 1, 1997 Issued
Array ( [id] => 1431771 [patent_doc_number] => 06516332 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Floating point number data processing means' [patent_app_type] => B1 [patent_app_number] => 08/921703 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1606 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516332.pdf [firstpage_image] =>[orig_patent_app_number] => 08921703 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921703
Floating point number data processing means Sep 1, 1997 Issued
Array ( [id] => 3968486 [patent_doc_number] => 05948053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Digital signal processor architecture using signal paths to carry out arithmetic operations' [patent_app_type] => 1 [patent_app_number] => 8/921193 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 8072 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/948/05948053.pdf [firstpage_image] =>[orig_patent_app_number] => 921193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/921193
Digital signal processor architecture using signal paths to carry out arithmetic operations Aug 28, 1997 Issued
Array ( [id] => 4235665 [patent_doc_number] => 06041337 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Linear function generator method with counter for implementation of control signals in digital logic' [patent_app_type] => 1 [patent_app_number] => 8/980358 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6335 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041337.pdf [firstpage_image] =>[orig_patent_app_number] => 980358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980358
Linear function generator method with counter for implementation of control signals in digital logic Aug 27, 1997 Issued
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