Search

Richard L Sutton

Examiner (ID: 9451)

Most Active Art Unit
2137
Art Unit(s)
2137
Total Applications
36
Issued Applications
23
Pending Applications
0
Abandoned Applications
13

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11200110 [patent_doc_number] => 09430322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Device based wear leveling using intrinsic endurance' [patent_app_type] => utility [patent_app_number] => 13/565650 [patent_app_country] => US [patent_app_date] => 2012-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5820 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13565650 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/565650
Device based wear leveling using intrinsic endurance Aug 1, 2012 Issued
Array ( [id] => 8639631 [patent_doc_number] => 20130031434 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'SCAN TEST CIRCUIT WITH SCAN CLOCK' [patent_app_type] => utility [patent_app_number] => 13/548176 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2613 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13548176 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/548176
Scan test circuit with scan clock Jul 11, 2012 Issued
Array ( [id] => 9945891 [patent_doc_number] => 08995206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Device, method and computer readable program for accessing memory cells using shortened read attempts' [patent_app_type] => utility [patent_app_number] => 13/547091 [patent_app_country] => US [patent_app_date] => 2012-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 12729 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13547091 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/547091
Device, method and computer readable program for accessing memory cells using shortened read attempts Jul 11, 2012 Issued
Array ( [id] => 9871614 [patent_doc_number] => 08959406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-17 [patent_title] => 'Method for data packet processing at very high data rates and extremely poor transmission conditions' [patent_app_type] => utility [patent_app_number] => 13/545968 [patent_app_country] => US [patent_app_date] => 2012-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6417 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13545968 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/545968
Method for data packet processing at very high data rates and extremely poor transmission conditions Jul 9, 2012 Issued
Array ( [id] => 8608663 [patent_doc_number] => 20130013975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-10 [patent_title] => 'SYSTEM AND DEVICE' [patent_app_type] => utility [patent_app_number] => 13/542099 [patent_app_country] => US [patent_app_date] => 2012-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7075 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13542099 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/542099
SYSTEM AND DEVICE Jul 4, 2012 Abandoned
Array ( [id] => 13750899 [patent_doc_number] => 10168387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-01 [patent_title] => Integrated defect detection and location systems and methods in semiconductor chip devices [patent_app_type] => utility [patent_app_number] => 13/541063 [patent_app_country] => US [patent_app_date] => 2012-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 6430 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13541063 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/541063
Integrated defect detection and location systems and methods in semiconductor chip devices Jul 2, 2012 Issued
Array ( [id] => 10603802 [patent_doc_number] => 09324371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-26 [patent_title] => 'Systems and methods for multi-stage decoding processing' [patent_app_type] => utility [patent_app_number] => 13/539639 [patent_app_country] => US [patent_app_date] => 2012-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6022 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13539639 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/539639
Systems and methods for multi-stage decoding processing Jul 1, 2012 Issued
Array ( [id] => 9630053 [patent_doc_number] => 08799748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Non-volatile semiconductor memory device performing multi-level storage operation' [patent_app_type] => utility [patent_app_number] => 13/537350 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5370 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13537350 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/537350
Non-volatile semiconductor memory device performing multi-level storage operation Jun 28, 2012 Issued
Array ( [id] => 8588743 [patent_doc_number] => 20130007563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING ERROR CORRECTION FUNCTION AND MEMORY SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/538231 [patent_app_country] => US [patent_app_date] => 2012-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 11308 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13538231 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/538231
SEMICONDUCTOR MEMORY DEVICE HAVING ERROR CORRECTION FUNCTION AND MEMORY SYSTEM INCLUDING THE SAME Jun 28, 2012 Abandoned
Array ( [id] => 10847801 [patent_doc_number] => 08875002 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-28 [patent_title] => 'Low cost adjacent double error correcting code' [patent_app_type] => utility [patent_app_number] => 13/535541 [patent_app_country] => US [patent_app_date] => 2012-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13535541 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/535541
Low cost adjacent double error correcting code Jun 27, 2012 Issued
Array ( [id] => 10873330 [patent_doc_number] => 08898551 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-25 [patent_title] => 'Reduced matrix Reed-Solomon encoding' [patent_app_type] => utility [patent_app_number] => 13/530683 [patent_app_country] => US [patent_app_date] => 2012-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5284 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13530683 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/530683
Reduced matrix Reed-Solomon encoding Jun 21, 2012 Issued
Array ( [id] => 9264883 [patent_doc_number] => 20130346812 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'WEAR LEVELING MEMORY USING ERROR RATE' [patent_app_type] => utility [patent_app_number] => 13/531139 [patent_app_country] => US [patent_app_date] => 2012-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6148 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13531139 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/531139
WEAR LEVELING MEMORY USING ERROR RATE Jun 21, 2012 Abandoned
Array ( [id] => 10150795 [patent_doc_number] => 09183085 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-10 [patent_title] => 'Systems and methods for adaptively selecting from among a plurality of error correction coding schemes in a flash drive for robustness and low latency' [patent_app_type] => utility [patent_app_number] => 13/477600 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 37114 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477600 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477600
Systems and methods for adaptively selecting from among a plurality of error correction coding schemes in a flash drive for robustness and low latency May 21, 2012 Issued
Array ( [id] => 10144003 [patent_doc_number] => 09176812 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-03 [patent_title] => 'Systems and methods for storing data in page stripes of a flash drive' [patent_app_type] => utility [patent_app_number] => 13/477568 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 37149 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 491 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477568 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477568
Systems and methods for storing data in page stripes of a flash drive May 21, 2012 Issued
Array ( [id] => 9974299 [patent_doc_number] => 09021336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-04-28 [patent_title] => 'Systems and methods for redundantly storing error correction codes in a flash drive with secondary parity information spread out across each page of a group of pages' [patent_app_type] => utility [patent_app_number] => 13/477598 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 37117 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477598 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477598
Systems and methods for redundantly storing error correction codes in a flash drive with secondary parity information spread out across each page of a group of pages May 21, 2012 Issued
Array ( [id] => 9611722 [patent_doc_number] => 08788910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-22 [patent_title] => 'Systems and methods for low latency, high reliability error correction in a flash drive' [patent_app_type] => utility [patent_app_number] => 13/477595 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 37122 [patent_no_of_claims] => 69 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477595 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477595
Systems and methods for low latency, high reliability error correction in a flash drive May 21, 2012 Issued
Array ( [id] => 9947630 [patent_doc_number] => 08996957 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-03-31 [patent_title] => 'Systems and methods for initializing regions of a flash drive having diverse error correction coding (ECC) schemes' [patent_app_type] => utility [patent_app_number] => 13/477633 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 37072 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477633 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477633
Systems and methods for initializing regions of a flash drive having diverse error correction coding (ECC) schemes May 21, 2012 Issued
Array ( [id] => 9176433 [patent_doc_number] => 20130318418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'ADAPTIVE ERROR CORRECTION FOR PHASE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/477610 [patent_app_country] => US [patent_app_date] => 2012-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7149 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13477610 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/477610
ADAPTIVE ERROR CORRECTION FOR PHASE CHANGE MEMORY May 21, 2012 Abandoned
Array ( [id] => 11359151 [patent_doc_number] => 09535804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-03 [patent_title] => 'Resiliency to memory failures in computer systems' [patent_app_type] => utility [patent_app_number] => 13/476819 [patent_app_country] => US [patent_app_date] => 2012-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9276 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13476819 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/476819
Resiliency to memory failures in computer systems May 20, 2012 Issued
Array ( [id] => 8349269 [patent_doc_number] => 20120210195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'METHOD, DEVICE, AND SYSTEM FOR FORWARD ERROR CORRECTION' [patent_app_type] => utility [patent_app_number] => 13/455549 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7633 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455549 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/455549
Method, device, and system for forward error correction Apr 24, 2012 Issued
Menu