Richard M. Lorence

Array ( [id] => 8318525 [patent_doc_number] => 08233312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'DRAM cell utilizing floating body effect and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/934745 [patent_app_country] => US [patent_app_date] => 2010-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 4448 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12934745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4645733 [patent_doc_number] => 08023344 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Data retention kill function' [patent_app_type] => utility [patent_app_number] => 12/827686 [patent_app_country] => US [patent_app_date] => 2010-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5659 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/023/08023344.pdf [firstpage_image] =>[orig_patent_app_number] => 12827686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6494846 [patent_doc_number] => 20100259982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'FLASH MEMORY DEVICE AND METHOD OF CONTROLLING FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/822246 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6145 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20100259982.pdf [firstpage_image] =>[orig_patent_app_number] => 12822246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6520237 [patent_doc_number] => 20100220518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'THERMALLY ASSISTED MULTI-BIT MRAM' [patent_app_type] => utility [patent_app_number] => 12/782101 [patent_app_country] => US [patent_app_date] => 2010-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3730 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20100220518.pdf [firstpage_image] =>[orig_patent_app_number] => 12782101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7585565 [patent_doc_number] => 20110280075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'MEMORY DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/780938 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 13469 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20110280075.pdf [firstpage_image] =>[orig_patent_app_number] => 12780938 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6588234 [patent_doc_number] => 20100321998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 12/780978 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20100321998.pdf [firstpage_image] =>[orig_patent_app_number] => 12780978 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6385169 [patent_doc_number] => 20100302877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'MEMORY DEVICE HAVING REDUCED STANDBY CURRENT AND MEMORY SYSTEM INCLUDING SAME' [patent_app_type] => utility [patent_app_number] => 12/780974 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5117 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20100302877.pdf [firstpage_image] =>[orig_patent_app_number] => 12780974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8423185 [patent_doc_number] => 08279676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Method of operating nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 12/780492 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3455 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12780492 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6210857 [patent_doc_number] => 20110134704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/780192 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10819 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20110134704.pdf [firstpage_image] =>[orig_patent_app_number] => 12780192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8702713 [patent_doc_number] => 08395940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Page buffer circuit, nonvolatile memory device including the page buffer circuit, and method of operating the nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 12/780140 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7094 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12780140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8147957 [patent_doc_number] => 08164973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-24 [patent_title] => 'Storage apparatus and method of controlling storage apparatus' [patent_app_type] => utility [patent_app_number] => 12/780004 [patent_app_country] => US [patent_app_date] => 2010-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5793 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/164/08164973.pdf [firstpage_image] =>[orig_patent_app_number] => 12780004 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8423196 [patent_doc_number] => 08279687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Single supply sub VDD bit-line precharge SRAM and method for level shifting' [patent_app_type] => utility [patent_app_number] => 12/779608 [patent_app_country] => US [patent_app_date] => 2010-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2321 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12779608 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5934684 [patent_doc_number] => 20110211397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'PIPE LATCH CIRCUIT AND METHOD FOR OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/779310 [patent_app_country] => US [patent_app_date] => 2010-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3426 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20110211397.pdf [firstpage_image] =>[orig_patent_app_number] => 12779310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4435848 [patent_doc_number] => 07969766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/772905 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 12708 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 505 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969766.pdf [firstpage_image] =>[orig_patent_app_number] => 12772905 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4645718 [patent_doc_number] => 08023329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-20 [patent_title] => 'Reducing effects of program disturb in a memory device' [patent_app_type] => utility [patent_app_number] => 12/763574 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3305 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/023/08023329.pdf [firstpage_image] =>[orig_patent_app_number] => 12763574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6508269 [patent_doc_number] => 20100202202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'ADJUSTING FOR CHARGE LOSS IN A MEMORY' [patent_app_type] => utility [patent_app_number] => 12/763613 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 11732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0202/20100202202.pdf [firstpage_image] =>[orig_patent_app_number] => 12763613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5951149 [patent_doc_number] => 20110032782 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-10 [patent_title] => 'Test method and device for memory device' [patent_app_type] => utility [patent_app_number] => 12/662270 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9030 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0032/20110032782.pdf [firstpage_image] =>[orig_patent_app_number] => 12662270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5991811 [patent_doc_number] => 20110013464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'Semiconductor memory device having hierarchical bit line structure and method of driving the semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/662222 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6220 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20110013464.pdf [firstpage_image] =>[orig_patent_app_number] => 12662222 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6549566 [patent_doc_number] => 20100271868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'Phase change memory devices and memory systems including the same' [patent_app_type] => utility [patent_app_number] => 12/662180 [patent_app_country] => US [patent_app_date] => 2010-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7164 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20100271868.pdf [firstpage_image] =>[orig_patent_app_number] => 12662180 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8330107 [patent_doc_number] => 08238177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/662040 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7894 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12662040 [rel_patent_id] =>[rel_patent_doc_number] =>)