Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8556683 [patent_doc_number] => 08331161 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Semiconductor memory device having swap function for data output pads' [patent_app_type] => utility [patent_app_number] => 12/662018 [patent_app_country] => US [patent_app_date] => 2010-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5282 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12662018 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662018
Semiconductor memory device having swap function for data output pads Mar 28, 2010 Issued
Array ( [id] => 8353525 [patent_doc_number] => 08248860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-21 [patent_title] => 'Memory device using a variable resistive element' [patent_app_type] => utility [patent_app_number] => 12/659840 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 7576 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12659840 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659840
Memory device using a variable resistive element Mar 22, 2010 Issued
Array ( [id] => 6616894 [patent_doc_number] => 20100172055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'Three Dimensional Magnetic Memory and/or Recording Device' [patent_app_type] => utility [patent_app_number] => 12/726070 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3701 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20100172055.pdf [firstpage_image] =>[orig_patent_app_number] => 12726070 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726070
Three dimensional magnetic memory and/or recording device Mar 16, 2010 Issued
Array ( [id] => 6464643 [patent_doc_number] => 20100284221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-11 [patent_title] => 'Nonvolatile memory device and method for controlling word line or bit line thereof' [patent_app_type] => utility [patent_app_number] => 12/659690 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6677 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20100284221.pdf [firstpage_image] =>[orig_patent_app_number] => 12659690 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659690
Nonvolatile memory device and method for controlling word line or bit line thereof Mar 16, 2010 Issued
Array ( [id] => 6227700 [patent_doc_number] => 20100182849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'Synchronous semiconductor device and data processing system including the same' [patent_app_type] => utility [patent_app_number] => 12/659521 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20100182849.pdf [firstpage_image] =>[orig_patent_app_number] => 12659521 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659521
Synchronous semiconductor device and data processing system including the same Mar 10, 2010 Issued
Array ( [id] => 8534721 [patent_doc_number] => 08310880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-13 [patent_title] => 'Virtual channel support in a nonvolatile memory controller' [patent_app_type] => utility [patent_app_number] => 12/718944 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 15327 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12718944 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/718944
Virtual channel support in a nonvolatile memory controller Mar 4, 2010 Issued
Array ( [id] => 8271728 [patent_doc_number] => 08213248 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Semiconductor memory device having improved local input/output line precharge scheme' [patent_app_type] => utility [patent_app_number] => 12/659328 [patent_app_country] => US [patent_app_date] => 2010-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5029 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12659328 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659328
Semiconductor memory device having improved local input/output line precharge scheme Mar 3, 2010 Issued
Array ( [id] => 8295789 [patent_doc_number] => 08223576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Regulators regulating charge pump and memory circuits thereof' [patent_app_type] => utility [patent_app_number] => 12/716430 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5019 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12716430 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716430
Regulators regulating charge pump and memory circuits thereof Mar 2, 2010 Issued
Array ( [id] => 6627844 [patent_doc_number] => 20100226163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'Method of resistive memory programming and associated devices and materials' [patent_app_type] => utility [patent_app_number] => 12/660782 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5838 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20100226163.pdf [firstpage_image] =>[orig_patent_app_number] => 12660782 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/660782
Method of resistive memory programming and associated devices and materials Mar 2, 2010 Abandoned
Array ( [id] => 8084599 [patent_doc_number] => 08149627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Current sink system based on sample and hold for source side sensing' [patent_app_type] => utility [patent_app_number] => 12/716028 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7618 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/149/08149627.pdf [firstpage_image] =>[orig_patent_app_number] => 12716028 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716028
Current sink system based on sample and hold for source side sensing Mar 1, 2010 Issued
Array ( [id] => 8204642 [patent_doc_number] => 08189409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Readout circuit for rewritable memories and readout method for same' [patent_app_type] => utility [patent_app_number] => 12/716010 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9894 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/189/08189409.pdf [firstpage_image] =>[orig_patent_app_number] => 12716010 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716010
Readout circuit for rewritable memories and readout method for same Mar 1, 2010 Issued
Array ( [id] => 6520154 [patent_doc_number] => 20100220513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Bi-Directional Resistive Memory Devices and Related Memory Systems and Methods of Writing Data' [patent_app_type] => utility [patent_app_number] => 12/715742 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8966 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20100220513.pdf [firstpage_image] =>[orig_patent_app_number] => 12715742 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715742
Bi-directional resistive memory devices and related memory systems and methods of writing data Mar 1, 2010 Issued
Array ( [id] => 6337391 [patent_doc_number] => 20100328995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'METHODS AND APPARATUS FOR REDUCING DEFECT BITS IN PHASE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/715802 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11594 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0328/20100328995.pdf [firstpage_image] =>[orig_patent_app_number] => 12715802 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715802
Methods and apparatus for reducing defect bits in phase change memory Mar 1, 2010 Issued
Array ( [id] => 8084595 [patent_doc_number] => 08149623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-03 [patent_title] => 'Controller and non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/715772 [patent_app_country] => US [patent_app_date] => 2010-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4831 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/149/08149623.pdf [firstpage_image] =>[orig_patent_app_number] => 12715772 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/715772
Controller and non-volatile semiconductor memory device Mar 1, 2010 Issued
Array ( [id] => 6421277 [patent_doc_number] => 20100142268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'PROGRAMMING METHOD TO REDUCE GATE COUPLING INTERFERENCE FOR NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/702688 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9188 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20100142268.pdf [firstpage_image] =>[orig_patent_app_number] => 12702688 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/702688
Programming method to reduce gate coupling interference for non-volatile memory Feb 8, 2010 Issued
Array ( [id] => 7546710 [patent_doc_number] => 08054687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Systems and methods of providing programmable voltage and current reference devices' [patent_app_type] => utility [patent_app_number] => 12/691653 [patent_app_country] => US [patent_app_date] => 2010-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 9212 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/054/08054687.pdf [firstpage_image] =>[orig_patent_app_number] => 12691653 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/691653
Systems and methods of providing programmable voltage and current reference devices Jan 20, 2010 Issued
Array ( [id] => 8271711 [patent_doc_number] => 08213220 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Device and method of programming a magnetic memory element' [patent_app_type] => utility [patent_app_number] => 12/687608 [patent_app_country] => US [patent_app_date] => 2010-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 8222 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12687608 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/687608
Device and method of programming a magnetic memory element Jan 13, 2010 Issued
Array ( [id] => 8106531 [patent_doc_number] => 08154912 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-10 [patent_title] => 'Volatile memory elements with soft error upset immunity' [patent_app_type] => utility [patent_app_number] => 12/686597 [patent_app_country] => US [patent_app_date] => 2010-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9957 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/154/08154912.pdf [firstpage_image] =>[orig_patent_app_number] => 12686597 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/686597
Volatile memory elements with soft error upset immunity Jan 12, 2010 Issued
Array ( [id] => 6433142 [patent_doc_number] => 20100103726 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'PHASE CHANGE MEMORY DEVICES AND SYSTEMS, AND RELATED PROGRAMMING METHODS' [patent_app_type] => utility [patent_app_number] => 12/652842 [patent_app_country] => US [patent_app_date] => 2010-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 57 [patent_figures_cnt] => 57 [patent_no_of_words] => 24070 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20100103726.pdf [firstpage_image] =>[orig_patent_app_number] => 12652842 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/652842
Phase change memory devices and systems, and related programming methods Jan 5, 2010 Issued
Array ( [id] => 6180972 [patent_doc_number] => 20110122684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'VOLTAGE COMPENSATION CIRCUIT, MULTI-LEVEL MEMORY DEVICE WITH THE SAME, AND VOLTAGE COMPENSATION METHOD FOR READING THE MULTI-LEVEL MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/650544 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4588 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20110122684.pdf [firstpage_image] =>[orig_patent_app_number] => 12650544 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650544
Voltage compensation circuit, multi-level memory device with the same, and voltage compensation method for reading the multi-level memory device Dec 30, 2009 Issued
Menu