Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5396441 [patent_doc_number] => 20090316504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT FOR GENERATING ROW MAIN SIGNAL AND CONTROLLING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/346540 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4145 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0316/20090316504.pdf [firstpage_image] =>[orig_patent_app_number] => 12346540 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346540
Semiconductor integrated circuit for generating row main signal and controlling method thereof Dec 29, 2008 Issued
Array ( [id] => 6403405 [patent_doc_number] => 20100165692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'VARIABLE MEMORY REFRESH DEVICES AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/346542 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4216 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165692.pdf [firstpage_image] =>[orig_patent_app_number] => 12346542 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/346542
Variable memory refresh devices and methods Dec 29, 2008 Issued
Array ( [id] => 5341689 [patent_doc_number] => 20090180339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WITH THREE-DIMENSIONAL ARRAY AND REPAIR METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/336827 [patent_app_country] => US [patent_app_date] => 2008-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9514 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20090180339.pdf [firstpage_image] =>[orig_patent_app_number] => 12336827 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/336827
Semiconductor memory device with three-dimensional array and repair method thereof Dec 16, 2008 Issued
Array ( [id] => 4521252 [patent_doc_number] => 07933160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'High speed carbon nanotube memory' [patent_app_type] => utility [patent_app_number] => 12/334443 [patent_app_country] => US [patent_app_date] => 2008-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 58 [patent_no_of_words] => 15266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/933/07933160.pdf [firstpage_image] =>[orig_patent_app_number] => 12334443 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/334443
High speed carbon nanotube memory Dec 12, 2008 Issued
Array ( [id] => 26157 [patent_doc_number] => 07796422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-14 [patent_title] => 'Magnetic random access memory and write method of the same' [patent_app_type] => utility [patent_app_number] => 12/333472 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 9785 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/796/07796422.pdf [firstpage_image] =>[orig_patent_app_number] => 12333472 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/333472
Magnetic random access memory and write method of the same Dec 11, 2008 Issued
Array ( [id] => 6411815 [patent_doc_number] => 20100149856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'Writing Memory Cells Exhibiting Threshold Switch Behavior' [patent_app_type] => utility [patent_app_number] => 12/333518 [patent_app_country] => US [patent_app_date] => 2008-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3194 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20100149856.pdf [firstpage_image] =>[orig_patent_app_number] => 12333518 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/333518
Writing memory cells exhibiting threshold switch behavior Dec 11, 2008 Issued
Array ( [id] => 5526026 [patent_doc_number] => 20090196103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-06 [patent_title] => 'NON-VOLATILE MEMORY DEVICE HAVING CONFIGURABLE PAGE SIZE' [patent_app_type] => utility [patent_app_number] => 12/329929 [patent_app_country] => US [patent_app_date] => 2008-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14324 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20090196103.pdf [firstpage_image] =>[orig_patent_app_number] => 12329929 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/329929
Non-volatile memory device having configurable page size Dec 7, 2008 Issued
Array ( [id] => 5366249 [patent_doc_number] => 20090303808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/327404 [patent_app_country] => US [patent_app_date] => 2008-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20090303808.pdf [firstpage_image] =>[orig_patent_app_number] => 12327404 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/327404
Semiconductor memory device and operation method thereof Dec 2, 2008 Issued
Array ( [id] => 6361180 [patent_doc_number] => 20100074000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'Analog Access Circuit for Validating Chalcogenide Memory Cells' [patent_app_type] => utility [patent_app_number] => 12/525510 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1704 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20100074000.pdf [firstpage_image] =>[orig_patent_app_number] => 12525510 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/525510
Analog access circuit for validating chalcogenide memory cells Nov 25, 2008 Issued
Array ( [id] => 6605830 [patent_doc_number] => 20100002500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-07 [patent_title] => 'Read Reference Circuit for a Sense Amplifier Within a Chalcogenide Memory Device' [patent_app_type] => utility [patent_app_number] => 12/525482 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1785 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20100002500.pdf [firstpage_image] =>[orig_patent_app_number] => 12525482 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/525482
Read reference circuit for a sense amplifier within a chalcogenide memory device Nov 25, 2008 Issued
Array ( [id] => 4452851 [patent_doc_number] => 07965541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Non-volatile single-event upset tolerant latch circuit' [patent_app_type] => utility [patent_app_number] => 12/525458 [patent_app_country] => US [patent_app_date] => 2008-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1363 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/965/07965541.pdf [firstpage_image] =>[orig_patent_app_number] => 12525458 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/525458
Non-volatile single-event upset tolerant latch circuit Nov 24, 2008 Issued
Array ( [id] => 4584732 [patent_doc_number] => 07826294 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Memory with output control' [patent_app_type] => utility [patent_app_number] => 12/275701 [patent_app_country] => US [patent_app_date] => 2008-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 15470 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826294.pdf [firstpage_image] =>[orig_patent_app_number] => 12275701 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/275701
Memory with output control Nov 20, 2008 Issued
12/274973 MULTIPLE DATA PATH MEMORIES AND SYSTEMS Nov 19, 2008 Abandoned
Array ( [id] => 4438847 [patent_doc_number] => 07898884 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Semiconductor device and test method therefor' [patent_app_type] => utility [patent_app_number] => 12/292432 [patent_app_country] => US [patent_app_date] => 2008-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7993 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898884.pdf [firstpage_image] =>[orig_patent_app_number] => 12292432 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/292432
Semiconductor device and test method therefor Nov 18, 2008 Issued
Array ( [id] => 5451214 [patent_doc_number] => 20090067250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'MEMORY DEVICES WITH PAGE BUFFER HAVING DUAL REGISTERS AND METHOD OF USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/271557 [patent_app_country] => US [patent_app_date] => 2008-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8052 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20090067250.pdf [firstpage_image] =>[orig_patent_app_number] => 12271557 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/271557
Memory devices with page buffer having dual registers and method of using the same Nov 13, 2008 Issued
Array ( [id] => 186842 [patent_doc_number] => 07649802 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Method for controlling time point for data output in synchronous memory device' [patent_app_type] => utility [patent_app_number] => 12/269163 [patent_app_country] => US [patent_app_date] => 2008-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4176 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649802.pdf [firstpage_image] =>[orig_patent_app_number] => 12269163 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/269163
Method for controlling time point for data output in synchronous memory device Nov 11, 2008 Issued
Array ( [id] => 5271656 [patent_doc_number] => 20090075432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/268101 [patent_app_country] => US [patent_app_date] => 2008-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 12551 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20090075432.pdf [firstpage_image] =>[orig_patent_app_number] => 12268101 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/268101
Semiconductor memory device Nov 9, 2008 Issued
Array ( [id] => 5579741 [patent_doc_number] => 20090175087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-09 [patent_title] => 'METHOD OF VERIFYING PROGRAMMING OPERATION OF FLASH MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/247288 [patent_app_country] => US [patent_app_date] => 2008-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3212 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20090175087.pdf [firstpage_image] =>[orig_patent_app_number] => 12247288 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/247288
Method of verifying programming operation of flash memory device Oct 7, 2008 Issued
Array ( [id] => 6368277 [patent_doc_number] => 20100080071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'DATA STORAGE USING READ-MASK-WRITE OPERATION' [patent_app_type] => utility [patent_app_number] => 12/242590 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3150 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080071.pdf [firstpage_image] =>[orig_patent_app_number] => 12242590 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242590
Data storage using read-mask-write operation Sep 29, 2008 Issued
Array ( [id] => 6368151 [patent_doc_number] => 20100080047 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'SPIN CURRENT GENERATOR FOR STT-MRAM OR OTHER SPINTRONICS APPLICATIONS' [patent_app_type] => utility [patent_app_number] => 12/242228 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4650 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080047.pdf [firstpage_image] =>[orig_patent_app_number] => 12242228 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/242228
Spin current generator for STT-MRAM or other spintronics applications Sep 29, 2008 Issued
Menu