Richard M. Lorence

Array ( [id] => 4500922 [patent_doc_number] => 07957216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Common memory device for variable device width and scalable pre-fetch and page size' [patent_app_type] => utility [patent_app_number] => 12/241192 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3748 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/957/07957216.pdf [firstpage_image] =>[orig_patent_app_number] => 12241192 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6368159 [patent_doc_number] => 20100080049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'THERMALLY ASSISTED MULTI-BIT MRAM' [patent_app_type] => utility [patent_app_number] => 12/242254 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4475 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080049.pdf [firstpage_image] =>[orig_patent_app_number] => 12242254 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6368243 [patent_doc_number] => 20100080064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'BIT LINE BIAS FOR PROGRAMMING A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/242312 [patent_app_country] => US [patent_app_date] => 2008-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4773 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080064.pdf [firstpage_image] =>[orig_patent_app_number] => 12242312 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6368279 [patent_doc_number] => 20100080072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'METHODS AND SYSTEMS TO WRITE TO SOFT ERROR UPSET TOLERANT LATCHES' [patent_app_type] => utility [patent_app_number] => 12/240318 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3690 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080072.pdf [firstpage_image] =>[orig_patent_app_number] => 12240318 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4537635 [patent_doc_number] => 07924618 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Method of programming non-volatile memory device' [patent_app_type] => utility [patent_app_number] => 12/240638 [patent_app_country] => US [patent_app_date] => 2008-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 8032 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/924/07924618.pdf [firstpage_image] =>[orig_patent_app_number] => 12240638 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5335791 [patent_doc_number] => 20090052255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'PROGRAM AND ERASE METHODS FOR NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/191400 [patent_app_country] => US [patent_app_date] => 2008-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 12431 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20090052255.pdf [firstpage_image] =>[orig_patent_app_number] => 12191400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5402709 [patent_doc_number] => 20090238023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/191116 [patent_app_country] => US [patent_app_date] => 2008-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2147 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20090238023.pdf [firstpage_image] =>[orig_patent_app_number] => 12191116 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5321698 [patent_doc_number] => 20090059688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Single-ended read and differential write scheme' [patent_app_type] => utility [patent_app_number] => 12/190680 [patent_app_country] => US [patent_app_date] => 2008-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2986 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20090059688.pdf [firstpage_image] =>[orig_patent_app_number] => 12190680 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 66440 [patent_doc_number] => 07760541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-20 [patent_title] => 'Functional float mode screen to test for leakage defects on SRAM bitlines' [patent_app_type] => utility [patent_app_number] => 12/190242 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2699 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/760/07760541.pdf [firstpage_image] =>[orig_patent_app_number] => 12190242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5335754 [patent_doc_number] => 20090052218 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'SEMICONDUCTOR PACKAGE HAVING MEMORY DEVICES STACKED ON LOGIC DEVICE' [patent_app_type] => utility [patent_app_number] => 12/190224 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4089 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20090052218.pdf [firstpage_image] =>[orig_patent_app_number] => 12190224 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5426336 [patent_doc_number] => 20090085646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'MEASURING HIGH VOLTAGES IN AN INTEGRATED CIRCUIT USING A COMMON MEASUREMENT PAD' [patent_app_type] => utility [patent_app_number] => 12/190208 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085646.pdf [firstpage_image] =>[orig_patent_app_number] => 12190208 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 34954 [patent_doc_number] => 07791928 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Design structure, structure and method of using asymmetric junction engineered SRAM pass gates' [patent_app_type] => utility [patent_app_number] => 12/190040 [patent_app_country] => US [patent_app_date] => 2008-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4719 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791928.pdf [firstpage_image] =>[orig_patent_app_number] => 12190040 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5414972 [patent_doc_number] => 20090040859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'Backup for Volatile State Retention in the Absence of Primary Circuit Power' [patent_app_type] => utility [patent_app_number] => 12/188622 [patent_app_country] => US [patent_app_date] => 2008-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6468 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20090040859.pdf [firstpage_image] =>[orig_patent_app_number] => 12188622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5413821 [patent_doc_number] => 20090039708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-12 [patent_title] => 'Backup For Circuits Having Volatile States' [patent_app_type] => utility [patent_app_number] => 12/188694 [patent_app_country] => US [patent_app_date] => 2008-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6177 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20090039708.pdf [firstpage_image] =>[orig_patent_app_number] => 12188694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4790757 [patent_doc_number] => 20080291730 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/170543 [patent_app_country] => US [patent_app_date] => 2008-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3267 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20080291730.pdf [firstpage_image] =>[orig_patent_app_number] => 12170543 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 115591 [patent_doc_number] => 07715273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Synchronous semiconductor device and data processing system including the same' [patent_app_type] => utility [patent_app_number] => 12/216674 [patent_app_country] => US [patent_app_date] => 2008-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4507 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/715/07715273.pdf [firstpage_image] =>[orig_patent_app_number] => 12216674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5308851 [patent_doc_number] => 20090016132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Semiconductor memory devices, memory systems and computing systems including the same' [patent_app_type] => utility [patent_app_number] => 12/216664 [patent_app_country] => US [patent_app_date] => 2008-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4638 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20090016132.pdf [firstpage_image] =>[orig_patent_app_number] => 12216664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5308819 [patent_doc_number] => 20090016100 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'Multi-level phase change memory device and related methods' [patent_app_type] => utility [patent_app_number] => 12/216534 [patent_app_country] => US [patent_app_date] => 2008-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9380 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20090016100.pdf [firstpage_image] =>[orig_patent_app_number] => 12216534 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5270004 [patent_doc_number] => 20090073780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'Memory device for detecting bit line leakage current and method thereof' [patent_app_type] => utility [patent_app_number] => 12/216400 [patent_app_country] => US [patent_app_date] => 2008-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4542 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20090073780.pdf [firstpage_image] =>[orig_patent_app_number] => 12216400 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 115574 [patent_doc_number] => 07715263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-11 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/216272 [patent_app_country] => US [patent_app_date] => 2008-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4915 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/715/07715263.pdf [firstpage_image] =>[orig_patent_app_number] => 12216272 [rel_patent_id] =>[rel_patent_doc_number] =>)