Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4865298 [patent_doc_number] => 20080144357 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'Method for sensing a signal in a two-terminal memory array having leakage current' [patent_app_type] => utility [patent_app_number] => 12/072813 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 25497 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20080144357.pdf [firstpage_image] =>[orig_patent_app_number] => 12072813 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/072813
Method for sensing a signal in a two-terminal memory array having leakage current Feb 27, 2008 Issued
Array ( [id] => 360767 [patent_doc_number] => 07486579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-03 [patent_title] => 'Method for controlling a semiconductor apparatus' [patent_app_type] => utility [patent_app_number] => 12/073017 [patent_app_country] => US [patent_app_date] => 2008-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10571 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/486/07486579.pdf [firstpage_image] =>[orig_patent_app_number] => 12073017 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/073017
Method for controlling a semiconductor apparatus Feb 27, 2008 Issued
Array ( [id] => 4844591 [patent_doc_number] => 20080180999 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-31 [patent_title] => 'Method, system and circuit for operating a non-volatile memory array' [patent_app_type] => utility [patent_app_number] => 12/071749 [patent_app_country] => US [patent_app_date] => 2008-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4985 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20080180999.pdf [firstpage_image] =>[orig_patent_app_number] => 12071749 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/071749
Method, system and circuit for operating a non-volatile memory array Feb 25, 2008 Issued
Array ( [id] => 253680 [patent_doc_number] => 07580321 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Synchronous semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/071198 [patent_app_country] => US [patent_app_date] => 2008-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7466 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/580/07580321.pdf [firstpage_image] =>[orig_patent_app_number] => 12071198 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/071198
Synchronous semiconductor memory device Feb 18, 2008 Issued
Array ( [id] => 125518 [patent_doc_number] => 07706178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Programmable matrix array with phase-change material' [patent_app_type] => utility [patent_app_number] => 12/069092 [patent_app_country] => US [patent_app_date] => 2008-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 17584 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/706/07706178.pdf [firstpage_image] =>[orig_patent_app_number] => 12069092 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/069092
Programmable matrix array with phase-change material Feb 5, 2008 Issued
Array ( [id] => 4537755 [patent_doc_number] => 07924636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-12 [patent_title] => 'Electronic circuit device' [patent_app_type] => utility [patent_app_number] => 12/526576 [patent_app_country] => US [patent_app_date] => 2008-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3640 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/924/07924636.pdf [firstpage_image] =>[orig_patent_app_number] => 12526576 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/526576
Electronic circuit device Jan 28, 2008 Issued
Array ( [id] => 4831844 [patent_doc_number] => 20080130390 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Semiconductor storage apparatus' [patent_app_type] => utility [patent_app_number] => 12/003734 [patent_app_country] => US [patent_app_date] => 2007-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6236 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20080130390.pdf [firstpage_image] =>[orig_patent_app_number] => 12003734 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/003734
Semiconductor storage apparatus Dec 30, 2007 Issued
Array ( [id] => 5433906 [patent_doc_number] => 20090168492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'Two terminal nonvolatile memory using gate controlled diode elements' [patent_app_type] => utility [patent_app_number] => 12/003570 [patent_app_country] => US [patent_app_date] => 2007-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5040 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168492.pdf [firstpage_image] =>[orig_patent_app_number] => 12003570 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/003570
Two terminal nonvolatile memory using gate controlled diode elements Dec 27, 2007 Issued
Array ( [id] => 5494538 [patent_doc_number] => 20090262566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'MASK PROGRAMMABLE ANTI-FUSE ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/306114 [patent_app_country] => US [patent_app_date] => 2007-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 11893 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0262/20090262566.pdf [firstpage_image] =>[orig_patent_app_number] => 12306114 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/306114
Mask programmable anti-fuse architecture Dec 19, 2007 Issued
Array ( [id] => 4892037 [patent_doc_number] => 20080101134 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-01 [patent_title] => 'Self refresh control device' [patent_app_type] => utility [patent_app_number] => 12/000956 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3358 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20080101134.pdf [firstpage_image] =>[orig_patent_app_number] => 12000956 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000956
Self refresh control device Dec 18, 2007 Issued
Array ( [id] => 84225 [patent_doc_number] => 07746698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-29 [patent_title] => 'Programming in memory devices using source bitline voltage bias' [patent_app_type] => utility [patent_app_number] => 11/956032 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/746/07746698.pdf [firstpage_image] =>[orig_patent_app_number] => 11956032 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/956032
Programming in memory devices using source bitline voltage bias Dec 12, 2007 Issued
Array ( [id] => 7594609 [patent_doc_number] => 07626854 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-01 [patent_title] => '2-write 3-read SRAM design using a 12-T storage cell' [patent_app_type] => utility [patent_app_number] => 11/952087 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 6235 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626854.pdf [firstpage_image] =>[orig_patent_app_number] => 11952087 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/952087
2-write 3-read SRAM design using a 12-T storage cell Dec 5, 2007 Issued
Array ( [id] => 7594592 [patent_doc_number] => 07626871 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-01 [patent_title] => 'High-speed single-ended memory read circuit' [patent_app_type] => utility [patent_app_number] => 11/952085 [patent_app_country] => US [patent_app_date] => 2007-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 5608 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626871.pdf [firstpage_image] =>[orig_patent_app_number] => 11952085 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/952085
High-speed single-ended memory read circuit Dec 5, 2007 Issued
Array ( [id] => 204611 [patent_doc_number] => 07633815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Flexible word line boosting across VCC supply' [patent_app_type] => utility [patent_app_number] => 11/951263 [patent_app_country] => US [patent_app_date] => 2007-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/633/07633815.pdf [firstpage_image] =>[orig_patent_app_number] => 11951263 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/951263
Flexible word line boosting across VCC supply Dec 4, 2007 Issued
Array ( [id] => 4865302 [patent_doc_number] => 20080144361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'STATIC RANDOM ACCESS MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 11/948812 [patent_app_country] => US [patent_app_date] => 2007-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5159 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20080144361.pdf [firstpage_image] =>[orig_patent_app_number] => 11948812 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/948812
Static random access memory architecture Nov 29, 2007 Issued
Array ( [id] => 357097 [patent_doc_number] => 07489539 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/987180 [patent_app_country] => US [patent_app_date] => 2007-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 12653 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/489/07489539.pdf [firstpage_image] =>[orig_patent_app_number] => 11987180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/987180
Semiconductor memory device Nov 27, 2007 Issued
Array ( [id] => 34951 [patent_doc_number] => 07791926 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'SEU hardening circuit and method' [patent_app_type] => utility [patent_app_number] => 11/944434 [patent_app_country] => US [patent_app_date] => 2007-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5358 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791926.pdf [firstpage_image] =>[orig_patent_app_number] => 11944434 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/944434
SEU hardening circuit and method Nov 21, 2007 Issued
Array ( [id] => 4937617 [patent_doc_number] => 20080074934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'Detection of row-to-row shorts and other row decode defects in memory devices' [patent_app_type] => utility [patent_app_number] => 11/986235 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8393 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074934.pdf [firstpage_image] =>[orig_patent_app_number] => 11986235 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/986235
Detection of row-to-row shorts and other row decode defects in memory devices Nov 19, 2007 Issued
Array ( [id] => 46512 [patent_doc_number] => 07778063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Non-volatile resistance switching memories and methods of making same' [patent_app_type] => utility [patent_app_number] => 11/937479 [patent_app_country] => US [patent_app_date] => 2007-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 49 [patent_no_of_words] => 11254 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/778/07778063.pdf [firstpage_image] =>[orig_patent_app_number] => 11937479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/937479
Non-volatile resistance switching memories and methods of making same Nov 7, 2007 Issued
Array ( [id] => 5927850 [patent_doc_number] => 20110038198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-17 [patent_title] => 'ELECTRONIC DEVICES BASED ON CURRENT INDUCED MAGNETIZATION DYNAMICS IN SINGLE MAGNETIC LAYERS' [patent_app_type] => utility [patent_app_number] => 11/935392 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6629 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20110038198.pdf [firstpage_image] =>[orig_patent_app_number] => 11935392 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935392
Electronic devices based on current induced magnetization dynamics in single magnetic layers Nov 4, 2007 Issued
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