Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5359527 [patent_doc_number] => 20090034321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Magnetoresistive Element with a Biasing Layer' [patent_app_type] => utility [patent_app_number] => 11/832416 [patent_app_country] => US [patent_app_date] => 2007-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0034/20090034321.pdf [firstpage_image] =>[orig_patent_app_number] => 11832416 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/832416
Magnetoresistive Element with a Biasing Layer Jul 31, 2007 Abandoned
Array ( [id] => 186809 [patent_doc_number] => 07649782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-19 [patent_title] => 'Non-volatile memory having a dynamically adjustable soft program verify voltage level and method therefor' [patent_app_type] => utility [patent_app_number] => 11/831168 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/649/07649782.pdf [firstpage_image] =>[orig_patent_app_number] => 11831168 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/831168
Non-volatile memory having a dynamically adjustable soft program verify voltage level and method therefor Jul 30, 2007 Issued
Array ( [id] => 4590487 [patent_doc_number] => 07852682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Flash memory device and program method of flash memory device using different voltages' [patent_app_type] => utility [patent_app_number] => 11/830260 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6684 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/852/07852682.pdf [firstpage_image] =>[orig_patent_app_number] => 11830260 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830260
Flash memory device and program method of flash memory device using different voltages Jul 29, 2007 Issued
Array ( [id] => 312101 [patent_doc_number] => 07529137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Methods of operating bandgap engineered memory' [patent_app_type] => utility [patent_app_number] => 11/830582 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 48 [patent_figures_cnt] => 61 [patent_no_of_words] => 14655 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/529/07529137.pdf [firstpage_image] =>[orig_patent_app_number] => 11830582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830582
Methods of operating bandgap engineered memory Jul 29, 2007 Issued
Array ( [id] => 264758 [patent_doc_number] => 07570529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-04 [patent_title] => 'Sense amplifier circuit of semiconductor memory device and method of operating the same' [patent_app_type] => utility [patent_app_number] => 11/830142 [patent_app_country] => US [patent_app_date] => 2007-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5709 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/570/07570529.pdf [firstpage_image] =>[orig_patent_app_number] => 11830142 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/830142
Sense amplifier circuit of semiconductor memory device and method of operating the same Jul 29, 2007 Issued
Array ( [id] => 4732547 [patent_doc_number] => 20080049526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE WITH DATA AND LOCAL REDUNDANCY MEMORY CELL ARRAYS, AND REDUNDANCY METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 11/829854 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20080049526.pdf [firstpage_image] =>[orig_patent_app_number] => 11829854 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/829854
SEMICONDUCTOR MEMORY DEVICE WITH DATA AND LOCAL REDUNDANCY MEMORY CELL ARRAYS, AND REDUNDANCY METHOD THEREOF Jul 26, 2007 Abandoned
Array ( [id] => 187094 [patent_doc_number] => 07646636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Non-volatile memory with dynamic multi-mode operation' [patent_app_type] => utility [patent_app_number] => 11/829410 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 9278 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646636.pdf [firstpage_image] =>[orig_patent_app_number] => 11829410 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/829410
Non-volatile memory with dynamic multi-mode operation Jul 26, 2007 Issued
Array ( [id] => 4732563 [patent_doc_number] => 20080049542 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-28 [patent_title] => 'ADDRESS COUNTER FOR NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/829580 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4238 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20080049542.pdf [firstpage_image] =>[orig_patent_app_number] => 11829580 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/829580
ADDRESS COUNTER FOR NONVOLATILE MEMORY DEVICE Jul 26, 2007 Abandoned
Array ( [id] => 279070 [patent_doc_number] => 07558152 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Address counter for nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 11/829527 [patent_app_country] => US [patent_app_date] => 2007-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4239 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558152.pdf [firstpage_image] =>[orig_patent_app_number] => 11829527 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/829527
Address counter for nonvolatile memory device Jul 26, 2007 Issued
Array ( [id] => 4761161 [patent_doc_number] => 20080313387 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE CAPABLE OF READING DATA RELIABLY' [patent_app_type] => utility [patent_app_number] => 11/780656 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 17524 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20080313387.pdf [firstpage_image] =>[orig_patent_app_number] => 11780656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/780656
Semiconductor memory device capable of reading data reliably Jul 19, 2007 Issued
Array ( [id] => 4804672 [patent_doc_number] => 20080016261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'METHOD FOR CONTROLLING TIME POINT FOR DATA OUTPUT IN SYNCHRONOUS MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/774657 [patent_app_country] => US [patent_app_date] => 2007-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4175 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20080016261.pdf [firstpage_image] =>[orig_patent_app_number] => 11774657 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/774657
Method for controlling time point for data output in synchronous memory device Jul 8, 2007 Issued
Array ( [id] => 883080 [patent_doc_number] => 07355897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-08 [patent_title] => 'Methods to resolve hard-to-erase condition in charge trapping non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/773857 [patent_app_country] => US [patent_app_date] => 2007-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4713 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/355/07355897.pdf [firstpage_image] =>[orig_patent_app_number] => 11773857 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/773857
Methods to resolve hard-to-erase condition in charge trapping non-volatile memory Jul 4, 2007 Issued
Array ( [id] => 4801798 [patent_doc_number] => 20080013385 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-17 [patent_title] => 'ASYNCHRONOUS SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 11/764884 [patent_app_country] => US [patent_app_date] => 2007-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9882 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20080013385.pdf [firstpage_image] =>[orig_patent_app_number] => 11764884 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764884
Asynchronous semiconductor memory Jun 18, 2007 Issued
Array ( [id] => 4757996 [patent_doc_number] => 20080310222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY' [patent_app_type] => utility [patent_app_number] => 11/764450 [patent_app_country] => US [patent_app_date] => 2007-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8894 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20080310222.pdf [firstpage_image] =>[orig_patent_app_number] => 11764450 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764450
Programming rate identification and control in a solid state memory Jun 17, 2007 Issued
Array ( [id] => 4531478 [patent_doc_number] => 07952905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-31 [patent_title] => 'Data storage device using magnetic domain wall movement and method of operating the same' [patent_app_type] => utility [patent_app_number] => 11/764432 [patent_app_country] => US [patent_app_date] => 2007-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 8109 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/952/07952905.pdf [firstpage_image] =>[orig_patent_app_number] => 11764432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764432
Data storage device using magnetic domain wall movement and method of operating the same Jun 17, 2007 Issued
Array ( [id] => 144145 [patent_doc_number] => 07688616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'Device and method of programming a magnetic memory element' [patent_app_type] => utility [patent_app_number] => 11/764618 [patent_app_country] => US [patent_app_date] => 2007-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 8016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/688/07688616.pdf [firstpage_image] =>[orig_patent_app_number] => 11764618 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764618
Device and method of programming a magnetic memory element Jun 17, 2007 Issued
Array ( [id] => 237038 [patent_doc_number] => 07596021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Memory system including MLC flash memory' [patent_app_type] => utility [patent_app_number] => 11/764594 [patent_app_country] => US [patent_app_date] => 2007-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4337 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596021.pdf [firstpage_image] =>[orig_patent_app_number] => 11764594 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/764594
Memory system including MLC flash memory Jun 17, 2007 Issued
Array ( [id] => 4790748 [patent_doc_number] => 20080291721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-27 [patent_title] => 'METHOD AND SYSTEM FOR PROVIDING A SPIN TRANSFER DEVICE WITH IMPROVED SWITCHING CHARACTERISTICS' [patent_app_type] => utility [patent_app_number] => 11/763800 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8688 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0291/20080291721.pdf [firstpage_image] =>[orig_patent_app_number] => 11763800 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/763800
Method and system for providing a spin transfer device with improved switching characteristics Jun 14, 2007 Issued
Array ( [id] => 4750922 [patent_doc_number] => 20080158993 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND METHOD CAPABLE OF RE-VERIFYING A VERIFIED MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 11/763606 [patent_app_country] => US [patent_app_date] => 2007-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3756 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20080158993.pdf [firstpage_image] =>[orig_patent_app_number] => 11763606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/763606
Non-volatile memory device and method capable of re-verifying a verified memory cell Jun 14, 2007 Issued
Array ( [id] => 4758016 [patent_doc_number] => 20080310242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-18 [patent_title] => 'SYSTEMS FOR PROGRAMMABLE CHIP ENABLE AND CHIP ADDRESS IN SEMICONDUCTOR MEMORY' [patent_app_type] => utility [patent_app_number] => 11/763292 [patent_app_country] => US [patent_app_date] => 2007-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11569 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20080310242.pdf [firstpage_image] =>[orig_patent_app_number] => 11763292 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/763292
Systems for programmable chip enable and chip address in semiconductor memory Jun 13, 2007 Issued
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