Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 253655 [patent_doc_number] => 07580296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-25 [patent_title] => 'Load management for memory device' [patent_app_type] => utility [patent_app_number] => 11/694714 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4905 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/580/07580296.pdf [firstpage_image] =>[orig_patent_app_number] => 11694714 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694714
Load management for memory device Mar 29, 2007 Issued
Array ( [id] => 4717334 [patent_doc_number] => 20080239856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Method for Load-Based Voltage Generation' [patent_app_type] => utility [patent_app_number] => 11/694798 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5440 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20080239856.pdf [firstpage_image] =>[orig_patent_app_number] => 11694798 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694798
Method for load-based voltage generation Mar 29, 2007 Issued
Array ( [id] => 279047 [patent_doc_number] => 07558129 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-07 [patent_title] => 'Device with load-based voltage generation' [patent_app_type] => utility [patent_app_number] => 11/694760 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5573 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/558/07558129.pdf [firstpage_image] =>[orig_patent_app_number] => 11694760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694760
Device with load-based voltage generation Mar 29, 2007 Issued
Array ( [id] => 4717314 [patent_doc_number] => 20080239836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-02 [patent_title] => 'Method for Managing Electrical Load of an Electronic Device' [patent_app_type] => utility [patent_app_number] => 11/694746 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4659 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20080239836.pdf [firstpage_image] =>[orig_patent_app_number] => 11694746 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694746
Method for managing electrical load of an electronic device Mar 29, 2007 Issued
Array ( [id] => 5044783 [patent_doc_number] => 20070263455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Iterative Memory Cell Charging Based on Reference Cell Value' [patent_app_type] => utility [patent_app_number] => 11/694742 [patent_app_country] => US [patent_app_date] => 2007-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17993 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20070263455.pdf [firstpage_image] =>[orig_patent_app_number] => 11694742 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/694742
Iterative memory cell charging based on reference cell value Mar 29, 2007 Issued
Array ( [id] => 4796410 [patent_doc_number] => 20080007996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-10 [patent_title] => 'MAGNETIC STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 11/692160 [patent_app_country] => US [patent_app_date] => 2007-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4397 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20080007996.pdf [firstpage_image] =>[orig_patent_app_number] => 11692160 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/692160
Magnetic storage device Mar 26, 2007 Issued
Array ( [id] => 5061658 [patent_doc_number] => 20070223297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-09-27 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 11/723830 [patent_app_country] => US [patent_app_date] => 2007-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7638 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0223/20070223297.pdf [firstpage_image] =>[orig_patent_app_number] => 11723830 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723830
Semiconductor storage device Mar 21, 2007 Issued
Array ( [id] => 5246302 [patent_doc_number] => 20070242536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Reference potential generating circuit and semiconductor memory device having the same' [patent_app_type] => utility [patent_app_number] => 11/723655 [patent_app_country] => US [patent_app_date] => 2007-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9140 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242536.pdf [firstpage_image] =>[orig_patent_app_number] => 11723655 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723655
Reference potential generating circuit and semiconductor memory device having the same Mar 20, 2007 Issued
Array ( [id] => 346124 [patent_doc_number] => 07499316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-03 [patent_title] => 'Phase change memory devices and program methods' [patent_app_type] => utility [patent_app_number] => 11/723354 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4714 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/499/07499316.pdf [firstpage_image] =>[orig_patent_app_number] => 11723354 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723354
Phase change memory devices and program methods Mar 18, 2007 Issued
Array ( [id] => 4738512 [patent_doc_number] => 20080232164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-25 [patent_title] => 'METHOD FOR PROGRAMMING A MULTILEVEL MEMORY' [patent_app_type] => utility [patent_app_number] => 11/723352 [patent_app_country] => US [patent_app_date] => 2007-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2502 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20080232164.pdf [firstpage_image] =>[orig_patent_app_number] => 11723352 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/723352
Method for programming a multilevel memory Mar 18, 2007 Issued
Array ( [id] => 5164398 [patent_doc_number] => 20070285982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Memory array having a programmable word length, and method of operating same' [patent_app_type] => utility [patent_app_number] => 11/724552 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11984 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20070285982.pdf [firstpage_image] =>[orig_patent_app_number] => 11724552 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724552
Memory array having a programmable word length, and method of operating same Mar 14, 2007 Issued
Array ( [id] => 331493 [patent_doc_number] => 07511993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-31 [patent_title] => 'Phase change memory device and related programming method' [patent_app_type] => utility [patent_app_number] => 11/724268 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4407 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/511/07511993.pdf [firstpage_image] =>[orig_patent_app_number] => 11724268 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724268
Phase change memory device and related programming method Mar 14, 2007 Issued
Array ( [id] => 5164410 [patent_doc_number] => 20070285994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/724210 [patent_app_country] => US [patent_app_date] => 2007-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4524 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0285/20070285994.pdf [firstpage_image] =>[orig_patent_app_number] => 11724210 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/724210
Semiconductor memory device Mar 14, 2007 Issued
Array ( [id] => 4930807 [patent_doc_number] => 20080001582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Internal voltage generator of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/717662 [patent_app_country] => US [patent_app_date] => 2007-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1872 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20080001582.pdf [firstpage_image] =>[orig_patent_app_number] => 11717662 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/717662
Internal voltage generator of semiconductor device Mar 13, 2007 Issued
Array ( [id] => 377921 [patent_doc_number] => 07313025 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-12-25 [patent_title] => 'Flash memory erase verification systems and methods' [patent_app_type] => utility [patent_app_number] => 11/675246 [patent_app_country] => US [patent_app_date] => 2007-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3727 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313025.pdf [firstpage_image] =>[orig_patent_app_number] => 11675246 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/675246
Flash memory erase verification systems and methods Feb 14, 2007 Issued
Array ( [id] => 5118281 [patent_doc_number] => 20070139995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/705420 [patent_app_country] => US [patent_app_date] => 2007-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13254 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20070139995.pdf [firstpage_image] =>[orig_patent_app_number] => 11705420 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/705420
Semiconductor memory device Feb 12, 2007 Abandoned
Array ( [id] => 838496 [patent_doc_number] => 07394712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Semiconductor memory device performing self refresh operation' [patent_app_type] => utility [patent_app_number] => 11/648398 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2742 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394712.pdf [firstpage_image] =>[orig_patent_app_number] => 11648398 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648398
Semiconductor memory device performing self refresh operation Dec 28, 2006 Issued
Array ( [id] => 4931721 [patent_doc_number] => 20080002496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'Input/output line precharge circuit and semiconductor memory device including input/output line precharge circuit' [patent_app_type] => utility [patent_app_number] => 11/648444 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20080002496.pdf [firstpage_image] =>[orig_patent_app_number] => 11648444 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648444
Input/output line precharge circuit and semiconductor memory device including input/output line precharge circuit Dec 28, 2006 Issued
Array ( [id] => 593432 [patent_doc_number] => 07447097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'TRAS adjusting circuit for self-refresh mode in a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/648270 [patent_app_country] => US [patent_app_date] => 2006-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4311 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/447/07447097.pdf [firstpage_image] =>[orig_patent_app_number] => 11648270 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/648270
TRAS adjusting circuit for self-refresh mode in a semiconductor device Dec 28, 2006 Issued
Array ( [id] => 919732 [patent_doc_number] => 07324380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Method for trimming the temperature coefficient of a floating gate voltage reference' [patent_app_type] => utility [patent_app_number] => 11/611665 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8081 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/324/07324380.pdf [firstpage_image] =>[orig_patent_app_number] => 11611665 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/611665
Method for trimming the temperature coefficient of a floating gate voltage reference Dec 14, 2006 Issued
Menu