Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5833408 [patent_doc_number] => 20060245238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Dynamic RAM storage techniques' [patent_app_type] => utility [patent_app_number] => 11/451847 [patent_app_country] => US [patent_app_date] => 2006-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4724 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245238.pdf [firstpage_image] =>[orig_patent_app_number] => 11451847 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/451847
Dynamic RAM storage techniques Jun 11, 2006 Issued
Array ( [id] => 844929 [patent_doc_number] => 07388794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-17 [patent_title] => 'Individual I/O modulation in memory devices' [patent_app_type] => utility [patent_app_number] => 11/447272 [patent_app_country] => US [patent_app_date] => 2006-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3219 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/388/07388794.pdf [firstpage_image] =>[orig_patent_app_number] => 11447272 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/447272
Individual I/O modulation in memory devices Jun 5, 2006 Issued
Array ( [id] => 5856376 [patent_doc_number] => 20060227601 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'Memory cell with trenched gated thyristor' [patent_app_type] => utility [patent_app_number] => 11/444990 [patent_app_country] => US [patent_app_date] => 2006-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7324 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20060227601.pdf [firstpage_image] =>[orig_patent_app_number] => 11444990 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/444990
Memory cell with trenched gated thyristor May 31, 2006 Issued
Array ( [id] => 919742 [patent_doc_number] => 07324384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout' [patent_app_type] => utility [patent_app_number] => 11/442379 [patent_app_country] => US [patent_app_date] => 2006-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 83 [patent_no_of_words] => 20615 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/324/07324384.pdf [firstpage_image] =>[orig_patent_app_number] => 11442379 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/442379
Monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout May 25, 2006 Issued
Array ( [id] => 409944 [patent_doc_number] => 07286430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/409238 [patent_app_country] => US [patent_app_date] => 2006-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 39 [patent_no_of_words] => 32152 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286430.pdf [firstpage_image] =>[orig_patent_app_number] => 11409238 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/409238
Semiconductor device Apr 23, 2006 Issued
Array ( [id] => 5919566 [patent_doc_number] => 20060239097 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Semiconductor storage apparatus' [patent_app_type] => utility [patent_app_number] => 11/409088 [patent_app_country] => US [patent_app_date] => 2006-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20060239097.pdf [firstpage_image] =>[orig_patent_app_number] => 11409088 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/409088
Semiconductor storage apparatus Apr 23, 2006 Issued
Array ( [id] => 5919490 [patent_doc_number] => 20060239059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Memory array circuit with two-bit memory cells' [patent_app_type] => utility [patent_app_number] => 11/408114 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6049 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20060239059.pdf [firstpage_image] =>[orig_patent_app_number] => 11408114 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/408114
Memory array circuit with two-bit memory cells Apr 20, 2006 Issued
Array ( [id] => 919694 [patent_doc_number] => 07324366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Non-volatile memory architecture employing bipolar programmable resistance storage elements' [patent_app_type] => utility [patent_app_number] => 11/409440 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/324/07324366.pdf [firstpage_image] =>[orig_patent_app_number] => 11409440 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/409440
Non-volatile memory architecture employing bipolar programmable resistance storage elements Apr 20, 2006 Issued
Array ( [id] => 430107 [patent_doc_number] => 07269092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-09-11 [patent_title] => 'Circuitry and device for generating and adjusting selected word line voltage' [patent_app_type] => utility [patent_app_number] => 11/409164 [patent_app_country] => US [patent_app_date] => 2006-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 9186 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/269/07269092.pdf [firstpage_image] =>[orig_patent_app_number] => 11409164 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/409164
Circuitry and device for generating and adjusting selected word line voltage Apr 20, 2006 Issued
Array ( [id] => 596582 [patent_doc_number] => 07440322 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Method and system for flash memory devices' [patent_app_type] => utility [patent_app_number] => 11/407816 [patent_app_country] => US [patent_app_date] => 2006-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5963 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/440/07440322.pdf [firstpage_image] =>[orig_patent_app_number] => 11407816 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407816
Method and system for flash memory devices Apr 19, 2006 Issued
Array ( [id] => 5240990 [patent_doc_number] => 20070019481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-25 [patent_title] => 'Semiconductor memories with block-dedicated programmable latency register' [patent_app_type] => utility [patent_app_number] => 11/407024 [patent_app_country] => US [patent_app_date] => 2006-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 15287 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20070019481.pdf [firstpage_image] =>[orig_patent_app_number] => 11407024 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407024
Semiconductor memories with block-dedicated programmable latency register Apr 19, 2006 Issued
Array ( [id] => 5644123 [patent_doc_number] => 20060282578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-14 [patent_title] => 'Semiconductor memory device capable of checking a redundancy code and memory system and computer system having the same' [patent_app_type] => utility [patent_app_number] => 11/407028 [patent_app_country] => US [patent_app_date] => 2006-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4410 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0282/20060282578.pdf [firstpage_image] =>[orig_patent_app_number] => 11407028 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407028
Semiconductor memory device capable of checking a redundancy code and memory system and computer system having the same Apr 19, 2006 Issued
Array ( [id] => 5209326 [patent_doc_number] => 20070247910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'NAND erase block size trimming apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/407856 [patent_app_country] => US [patent_app_date] => 2006-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2990 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0247/20070247910.pdf [firstpage_image] =>[orig_patent_app_number] => 11407856 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407856
NAND erase block size trimming apparatus and method Apr 19, 2006 Abandoned
Array ( [id] => 5919491 [patent_doc_number] => 20060239060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Semiconductor memory device and method for operating the same' [patent_app_type] => utility [patent_app_number] => 11/405452 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4951 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20060239060.pdf [firstpage_image] =>[orig_patent_app_number] => 11405452 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/405452
Semiconductor memory device and method for operating the same Apr 17, 2006 Abandoned
Array ( [id] => 5919583 [patent_doc_number] => 20060239105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/405488 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9971 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20060239105.pdf [firstpage_image] =>[orig_patent_app_number] => 11405488 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/405488
Semiconductor memory device Apr 17, 2006 Issued
11/406116 LOW POWER HIGH DENSITY RANDOM ACCESS MEMORY FLASH CELLS AND ARRAYS Apr 17, 2006 Abandoned
Array ( [id] => 377946 [patent_doc_number] => 07313050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Word-line driver for memory devices' [patent_app_type] => utility [patent_app_number] => 11/406984 [patent_app_country] => US [patent_app_date] => 2006-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1988 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/313/07313050.pdf [firstpage_image] =>[orig_patent_app_number] => 11406984 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/406984
Word-line driver for memory devices Apr 17, 2006 Issued
Array ( [id] => 409902 [patent_doc_number] => 07286403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/402980 [patent_app_country] => US [patent_app_date] => 2006-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9403 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286403.pdf [firstpage_image] =>[orig_patent_app_number] => 11402980 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/402980
Non-volatile semiconductor memory device Apr 12, 2006 Issued
Array ( [id] => 5246264 [patent_doc_number] => 20070242498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Sub-threshold static random access memory' [patent_app_type] => utility [patent_app_number] => 11/403690 [patent_app_country] => US [patent_app_date] => 2006-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5380 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20070242498.pdf [firstpage_image] =>[orig_patent_app_number] => 11403690 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/403690
Sub-threshold static random access memory Apr 12, 2006 Abandoned
Array ( [id] => 5118296 [patent_doc_number] => 20070140010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Method and Apparatus for Operating a String of Charge Trapping Memory Cells' [patent_app_type] => utility [patent_app_number] => 11/279720 [patent_app_country] => US [patent_app_date] => 2006-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7206 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20070140010.pdf [firstpage_image] =>[orig_patent_app_number] => 11279720 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/279720
Method and apparatus for operating a string of charge trapping memory cells Apr 12, 2006 Issued
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