Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 449130 [patent_doc_number] => 07254080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-07 [patent_title] => 'Fuse circuit and electronic circuit' [patent_app_type] => utility [patent_app_number] => 11/355682 [patent_app_country] => US [patent_app_date] => 2006-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 4593 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/254/07254080.pdf [firstpage_image] =>[orig_patent_app_number] => 11355682 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/355682
Fuse circuit and electronic circuit Feb 15, 2006 Issued
Array ( [id] => 459637 [patent_doc_number] => 07245536 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-17 [patent_title] => 'Precision non-volatile CMOS reference circuit' [patent_app_type] => utility [patent_app_number] => 11/355394 [patent_app_country] => US [patent_app_date] => 2006-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5569 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245536.pdf [firstpage_image] =>[orig_patent_app_number] => 11355394 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/355394
Precision non-volatile CMOS reference circuit Feb 14, 2006 Issued
Array ( [id] => 5067963 [patent_doc_number] => 20070189064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'Multi-state thermally assisted storage' [patent_app_type] => utility [patent_app_number] => 11/353326 [patent_app_country] => US [patent_app_date] => 2006-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4838 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20070189064.pdf [firstpage_image] =>[orig_patent_app_number] => 11353326 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/353326
Multi-state thermally assisted storage Feb 13, 2006 Issued
Array ( [id] => 5068001 [patent_doc_number] => 20070189102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-16 [patent_title] => 'SRAM DEVICE WITH REDUCED LEAKAGE CURRENT' [patent_app_type] => utility [patent_app_number] => 11/353410 [patent_app_country] => US [patent_app_date] => 2006-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20070189102.pdf [firstpage_image] =>[orig_patent_app_number] => 11353410 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/353410
SRAM device with reduced leakage current Feb 12, 2006 Issued
Array ( [id] => 5840609 [patent_doc_number] => 20060120198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 11/336887 [patent_app_country] => US [patent_app_date] => 2006-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5497 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20060120198.pdf [firstpage_image] =>[orig_patent_app_number] => 11336887 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/336887
Nonvolatile memory Jan 22, 2006 Issued
Array ( [id] => 5187153 [patent_doc_number] => 20070165461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-19 [patent_title] => 'Disabling faulty flash memory dies' [patent_app_type] => utility [patent_app_number] => 11/334087 [patent_app_country] => US [patent_app_date] => 2006-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8100 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20070165461.pdf [firstpage_image] =>[orig_patent_app_number] => 11334087 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/334087
Disabling faulty flash memory dies Jan 17, 2006 Issued
Array ( [id] => 5595035 [patent_doc_number] => 20060158951 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Nonvolatile semiconductor memory device with wired-or structure blocking data transmission from defective page buffer' [patent_app_type] => utility [patent_app_number] => 11/333983 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20060158951.pdf [firstpage_image] =>[orig_patent_app_number] => 11333983 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/333983
Nonvolatile semiconductor memory device with wired-or structure blocking data transmission from defective page buffer Jan 16, 2006 Issued
Array ( [id] => 593337 [patent_doc_number] => 07447084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Semiconductor memory device and method of supplying wordline voltage thereof' [patent_app_type] => utility [patent_app_number] => 11/325102 [patent_app_country] => US [patent_app_date] => 2006-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2204 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/447/07447084.pdf [firstpage_image] =>[orig_patent_app_number] => 11325102 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/325102
Semiconductor memory device and method of supplying wordline voltage thereof Jan 3, 2006 Issued
Array ( [id] => 4987225 [patent_doc_number] => 20070153563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Write circuit for resistive memory' [patent_app_type] => utility [patent_app_number] => 11/324700 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5583 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20070153563.pdf [firstpage_image] =>[orig_patent_app_number] => 11324700 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324700
Integrated circuit having a resistive memory Jan 2, 2006 Issued
Array ( [id] => 887749 [patent_doc_number] => 07352627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-01 [patent_title] => 'Method, system, and circuit for operating a non-volatile memory array' [patent_app_type] => utility [patent_app_number] => 11/324718 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4951 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/352/07352627.pdf [firstpage_image] =>[orig_patent_app_number] => 11324718 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324718
Method, system, and circuit for operating a non-volatile memory array Jan 2, 2006 Issued
Array ( [id] => 5630124 [patent_doc_number] => 20060146592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-06 [patent_title] => 'Ferroelectric random access memory device and method for driving the same' [patent_app_type] => utility [patent_app_number] => 11/324560 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6559 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20060146592.pdf [firstpage_image] =>[orig_patent_app_number] => 11324560 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/324560
Ferroelectric random access memory device and method for driving the same Jan 2, 2006 Issued
Array ( [id] => 445207 [patent_doc_number] => 07257038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-14 [patent_title] => 'Test mode for IPP current measurement for wordline defect detection' [patent_app_type] => utility [patent_app_number] => 11/322252 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3066 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/257/07257038.pdf [firstpage_image] =>[orig_patent_app_number] => 11322252 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/322252
Test mode for IPP current measurement for wordline defect detection Jan 2, 2006 Issued
Array ( [id] => 482302 [patent_doc_number] => 07224610 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-05-29 [patent_title] => 'Layout reduction by sharing a column latch per two bit lines' [patent_app_type] => utility [patent_app_number] => 11/325132 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4869 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/224/07224610.pdf [firstpage_image] =>[orig_patent_app_number] => 11325132 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/325132
Layout reduction by sharing a column latch per two bit lines Jan 2, 2006 Issued
Array ( [id] => 916567 [patent_doc_number] => 07327626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-05 [patent_title] => 'Self refresh control device' [patent_app_type] => utility [patent_app_number] => 11/318594 [patent_app_country] => US [patent_app_date] => 2005-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3353 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/327/07327626.pdf [firstpage_image] =>[orig_patent_app_number] => 11318594 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/318594
Self refresh control device Dec 27, 2005 Issued
Array ( [id] => 5055507 [patent_doc_number] => 20070058428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Nonvolatile semiconductor memory device having uniform operational characteristics for memory cells' [patent_app_type] => utility [patent_app_number] => 11/317300 [patent_app_country] => US [patent_app_date] => 2005-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3788 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20070058428.pdf [firstpage_image] =>[orig_patent_app_number] => 11317300 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317300
Nonvolatile semiconductor memory device having uniform operational characteristics for memory cells Dec 26, 2005 Issued
Array ( [id] => 887811 [patent_doc_number] => 07352647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-01 [patent_title] => 'Reduced power usage in a memory for a programmable logic device' [patent_app_type] => utility [patent_app_number] => 11/317324 [patent_app_country] => US [patent_app_date] => 2005-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6139 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/352/07352647.pdf [firstpage_image] =>[orig_patent_app_number] => 11317324 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/317324
Reduced power usage in a memory for a programmable logic device Dec 21, 2005 Issued
Array ( [id] => 554023 [patent_doc_number] => 07164605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Semiconductor memory device and electric device with the same' [patent_app_type] => utility [patent_app_number] => 11/305193 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 5752 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/164/07164605.pdf [firstpage_image] =>[orig_patent_app_number] => 11305193 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305193
Semiconductor memory device and electric device with the same Dec 18, 2005 Issued
Array ( [id] => 657306 [patent_doc_number] => 07110318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/305043 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 10859 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/110/07110318.pdf [firstpage_image] =>[orig_patent_app_number] => 11305043 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305043
Semiconductor memory device Dec 18, 2005 Issued
Array ( [id] => 5812181 [patent_doc_number] => 20060083055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Providing a reference voltage to a cross point memory array' [patent_app_type] => utility [patent_app_number] => 11/288472 [patent_app_country] => US [patent_app_date] => 2005-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7723 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083055.pdf [firstpage_image] =>[orig_patent_app_number] => 11288472 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/288472
Providing a reference voltage to a cross point memory array Nov 27, 2005 Issued
Array ( [id] => 5812189 [patent_doc_number] => 20060083063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Memory devices with page buffer having dual registers and method of using the same' [patent_app_type] => utility [patent_app_number] => 11/284604 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 8002 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20060083063.pdf [firstpage_image] =>[orig_patent_app_number] => 11284604 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/284604
Memory devices with page buffer having dual registers and method of using the same Nov 20, 2005 Issued
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