Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 741530 [patent_doc_number] => 07035135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/207938 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 27 [patent_no_of_words] => 12596 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035135.pdf [firstpage_image] =>[orig_patent_app_number] => 11207938 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207938
Semiconductor memory device Aug 21, 2005 Issued
Array ( [id] => 5589747 [patent_doc_number] => 20060039198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Bitline governed approach for coarse/fine programming' [patent_app_type] => utility [patent_app_number] => 11/207427 [patent_app_country] => US [patent_app_date] => 2005-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15842 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20060039198.pdf [firstpage_image] =>[orig_patent_app_number] => 11207427 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207427
Bitline governed approach for coarse/fine programming Aug 17, 2005 Issued
Array ( [id] => 5709216 [patent_doc_number] => 20060050561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-09 [patent_title] => 'Bitline governed approach for program control of non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/207260 [patent_app_country] => US [patent_app_date] => 2005-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 15832 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20060050561.pdf [firstpage_image] =>[orig_patent_app_number] => 11207260 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/207260
Bitline governed approach for programming non-volatile memory Aug 17, 2005 Issued
Array ( [id] => 5589758 [patent_doc_number] => 20060039209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Semiconductor memory' [patent_app_type] => utility [patent_app_number] => 11/202230 [patent_app_country] => US [patent_app_date] => 2005-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9674 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20060039209.pdf [firstpage_image] =>[orig_patent_app_number] => 11202230 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/202230
Semiconductor memory Aug 11, 2005 Issued
Array ( [id] => 542877 [patent_doc_number] => 07180786 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-20 [patent_title] => 'Row decoder for NAND memories' [patent_app_type] => utility [patent_app_number] => 11/202632 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5804 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/180/07180786.pdf [firstpage_image] =>[orig_patent_app_number] => 11202632 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/202632
Row decoder for NAND memories Aug 10, 2005 Issued
Array ( [id] => 531545 [patent_doc_number] => 07187586 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-03-06 [patent_title] => 'Flash memory erase verification systems and methods' [patent_app_type] => utility [patent_app_number] => 11/201620 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3714 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187586.pdf [firstpage_image] =>[orig_patent_app_number] => 11201620 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201620
Flash memory erase verification systems and methods Aug 10, 2005 Issued
Array ( [id] => 5589725 [patent_doc_number] => 20060039176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Memory cell' [patent_app_type] => utility [patent_app_number] => 11/201168 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4816 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20060039176.pdf [firstpage_image] =>[orig_patent_app_number] => 11201168 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201168
Static random access memory (SRAM) cell Aug 10, 2005 Issued
Array ( [id] => 409924 [patent_doc_number] => 07286419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Semiconductor memory device outputting identifying and roll call information' [patent_app_type] => utility [patent_app_number] => 11/200012 [patent_app_country] => US [patent_app_date] => 2005-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3550 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286419.pdf [firstpage_image] =>[orig_patent_app_number] => 11200012 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/200012
Semiconductor memory device outputting identifying and roll call information Aug 9, 2005 Issued
Array ( [id] => 471272 [patent_doc_number] => 07233514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-06-19 [patent_title] => 'Non-volatile semiconductor memory and method for reading a memory cell' [patent_app_type] => utility [patent_app_number] => 11/200504 [patent_app_country] => US [patent_app_date] => 2005-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5790 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/233/07233514.pdf [firstpage_image] =>[orig_patent_app_number] => 11200504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/200504
Non-volatile semiconductor memory and method for reading a memory cell Aug 8, 2005 Issued
Array ( [id] => 5825400 [patent_doc_number] => 20060062071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/198334 [patent_app_country] => US [patent_app_date] => 2005-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9594 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20060062071.pdf [firstpage_image] =>[orig_patent_app_number] => 11198334 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/198334
Semiconductor memory device having a plurality of latch circuits coupled to each read amplifier Aug 7, 2005 Issued
Array ( [id] => 5050175 [patent_doc_number] => 20070030719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'One time programmable memory and method of operation' [patent_app_type] => utility [patent_app_number] => 11/197814 [patent_app_country] => US [patent_app_date] => 2005-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20070030719.pdf [firstpage_image] =>[orig_patent_app_number] => 11197814 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197814
One time programmable memory and method of operation Aug 4, 2005 Issued
Array ( [id] => 621677 [patent_doc_number] => 07142453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Semiconductor memory device and memory card' [patent_app_type] => utility [patent_app_number] => 11/196460 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 6256 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/142/07142453.pdf [firstpage_image] =>[orig_patent_app_number] => 11196460 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/196460
Semiconductor memory device and memory card Aug 3, 2005 Issued
Array ( [id] => 125519 [patent_doc_number] => 07706179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Three dimensional magnetic memory and/or recording device' [patent_app_type] => utility [patent_app_number] => 11/197377 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3706 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/706/07706179.pdf [firstpage_image] =>[orig_patent_app_number] => 11197377 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197377
Three dimensional magnetic memory and/or recording device Aug 3, 2005 Issued
Array ( [id] => 214010 [patent_doc_number] => RE040976 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2009-11-17 [patent_title] => 'Common source EEPROM and flash memory' [patent_app_type] => reissue [patent_app_number] => 11/198860 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 9360 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/040/RE040976.pdf [firstpage_image] =>[orig_patent_app_number] => 11198860 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/198860
Common source EEPROM and flash memory Aug 3, 2005 Issued
Array ( [id] => 5050198 [patent_doc_number] => 20070030742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-02-08 [patent_title] => 'Combination column redundancy system for a memory array' [patent_app_type] => utility [patent_app_number] => 11/195878 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8324 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20070030742.pdf [firstpage_image] =>[orig_patent_app_number] => 11195878 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/195878
Combination column redundancy system for a memory array Aug 1, 2005 Issued
Array ( [id] => 451396 [patent_doc_number] => 07251191 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-31 [patent_title] => 'Method for controlling time point for data output in synchronous memory device' [patent_app_type] => utility [patent_app_number] => 11/194934 [patent_app_country] => US [patent_app_date] => 2005-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4171 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/251/07251191.pdf [firstpage_image] =>[orig_patent_app_number] => 11194934 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/194934
Method for controlling time point for data output in synchronous memory device Aug 1, 2005 Issued
Array ( [id] => 7229748 [patent_doc_number] => 20050255638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'Trench corner effect bidirectional flash memory cell' [patent_app_type] => utility [patent_app_number] => 11/188497 [patent_app_country] => US [patent_app_date] => 2005-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2769 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0255/20050255638.pdf [firstpage_image] =>[orig_patent_app_number] => 11188497 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/188497
Trench corner effect bidirectional flash memory cell Jul 24, 2005 Issued
Array ( [id] => 838488 [patent_doc_number] => 07394707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Programmable data strobe enable architecture for DDR memory applications' [patent_app_type] => utility [patent_app_number] => 11/166292 [patent_app_country] => US [patent_app_date] => 2005-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2927 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/394/07394707.pdf [firstpage_image] =>[orig_patent_app_number] => 11166292 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/166292
Programmable data strobe enable architecture for DDR memory applications Jun 23, 2005 Issued
Array ( [id] => 499073 [patent_doc_number] => 07212454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Method and apparatus for programming a memory array' [patent_app_type] => utility [patent_app_number] => 11/158396 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4121 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212454.pdf [firstpage_image] =>[orig_patent_app_number] => 11158396 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/158396
Method and apparatus for programming a memory array Jun 21, 2005 Issued
Array ( [id] => 459699 [patent_doc_number] => 07245552 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-07-17 [patent_title] => 'Parallel data path architecture' [patent_app_type] => utility [patent_app_number] => 11/157868 [patent_app_country] => US [patent_app_date] => 2005-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4956 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/245/07245552.pdf [firstpage_image] =>[orig_patent_app_number] => 11157868 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/157868
Parallel data path architecture Jun 21, 2005 Issued
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