Search

Richard M. Lorence

Examiner (ID: 3825, Phone: (571)272-7094 , Office: P/3655 )

Most Active Art Unit
3502
Art Unit(s)
3502, 3617, 3622, 0, 3655, 3656, 3681
Total Applications
3174
Issued Applications
2769
Pending Applications
79
Abandoned Applications
335

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 498921 [patent_doc_number] => 07212433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Ferromagnetic layer compositions and structures for spin polarized memory devices, including memory devices' [patent_app_type] => utility [patent_app_number] => 10/962253 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 9889 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212433.pdf [firstpage_image] =>[orig_patent_app_number] => 10962253 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/962253
Ferromagnetic layer compositions and structures for spin polarized memory devices, including memory devices Oct 7, 2004 Issued
Array ( [id] => 7009523 [patent_doc_number] => 20050063239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Magnetic spin based memory with semiconductor selector' [patent_app_type] => utility [patent_app_number] => 10/962254 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9900 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20050063239.pdf [firstpage_image] =>[orig_patent_app_number] => 10962254 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/962254
Magnetic spin based memory with semiconductor selector Oct 7, 2004 Issued
Array ( [id] => 723411 [patent_doc_number] => 07050329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-23 [patent_title] => 'Magnetic spin based memory with inductive write lines' [patent_app_type] => utility [patent_app_number] => 10/962252 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9904 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/050/07050329.pdf [firstpage_image] =>[orig_patent_app_number] => 10962252 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/962252
Magnetic spin based memory with inductive write lines Oct 7, 2004 Issued
Array ( [id] => 7220425 [patent_doc_number] => 20050077582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 10/957712 [patent_app_country] => US [patent_app_date] => 2004-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9866 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077582.pdf [firstpage_image] =>[orig_patent_app_number] => 10957712 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/957712
Semiconductor integrated circuit device Oct 4, 2004 Issued
Array ( [id] => 977314 [patent_doc_number] => 06934195 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Method and system for efficiently reading and programming of dual cell memory elements' [patent_app_type] => utility [patent_app_number] => 10/931616 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6023 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/934/06934195.pdf [firstpage_image] =>[orig_patent_app_number] => 10931616 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931616
Method and system for efficiently reading and programming of dual cell memory elements Aug 30, 2004 Issued
Array ( [id] => 947185 [patent_doc_number] => 06965520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-15 [patent_title] => 'Delay system for generating control signals in ferroelectric memory devices' [patent_app_type] => utility [patent_app_number] => 10/910508 [patent_app_country] => US [patent_app_date] => 2004-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 10263 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/965/06965520.pdf [firstpage_image] =>[orig_patent_app_number] => 10910508 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/910508
Delay system for generating control signals in ferroelectric memory devices Aug 2, 2004 Issued
Array ( [id] => 7619119 [patent_doc_number] => 06944070 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-13 [patent_title] => 'Integrated circuit devices having high precision digital delay lines therein' [patent_app_type] => utility [patent_app_number] => 10/880893 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 13893 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944070.pdf [firstpage_image] =>[orig_patent_app_number] => 10880893 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880893
Integrated circuit devices having high precision digital delay lines therein Jun 29, 2004 Issued
Array ( [id] => 490071 [patent_doc_number] => 07218550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-15 [patent_title] => 'Magnetic storage device' [patent_app_type] => utility [patent_app_number] => 10/874205 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4452 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/218/07218550.pdf [firstpage_image] =>[orig_patent_app_number] => 10874205 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/874205
Magnetic storage device Jun 23, 2004 Issued
Array ( [id] => 7237392 [patent_doc_number] => 20050270853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Memory module and method for accessing the same' [patent_app_type] => utility [patent_app_number] => 10/860142 [patent_app_country] => US [patent_app_date] => 2004-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2185 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20050270853.pdf [firstpage_image] =>[orig_patent_app_number] => 10860142 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/860142
Memory module and method for accessing the same Jun 3, 2004 Abandoned
Array ( [id] => 7342449 [patent_doc_number] => 20040246759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Semiconductor storage device' [patent_app_type] => new [patent_app_number] => 10/859187 [patent_app_country] => US [patent_app_date] => 2004-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6167 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20040246759.pdf [firstpage_image] =>[orig_patent_app_number] => 10859187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/859187
Semiconductor storage device Jun 2, 2004 Issued
Array ( [id] => 714018 [patent_doc_number] => 07057955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Dynamically unbalanced sense amplifier' [patent_app_type] => utility [patent_app_number] => 10/860080 [patent_app_country] => US [patent_app_date] => 2004-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3451 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057955.pdf [firstpage_image] =>[orig_patent_app_number] => 10860080 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/860080
Dynamically unbalanced sense amplifier Jun 2, 2004 Issued
Array ( [id] => 7342494 [patent_doc_number] => 20040246772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Method and semiconductor integrated circuit for detecting soft defects in static memory cell' [patent_app_type] => new [patent_app_number] => 10/858984 [patent_app_country] => US [patent_app_date] => 2004-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2703 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20040246772.pdf [firstpage_image] =>[orig_patent_app_number] => 10858984 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/858984
Method and semiconductor integrated circuit for detecting soft defects in static memory cell Jun 1, 2004 Abandoned
Array ( [id] => 7237358 [patent_doc_number] => 20050270849 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-08 [patent_title] => 'Program/erase method for p-channel charge trapping memory device' [patent_app_type] => utility [patent_app_number] => 10/857866 [patent_app_country] => US [patent_app_date] => 2004-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5503 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0270/20050270849.pdf [firstpage_image] =>[orig_patent_app_number] => 10857866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/857866
Program/erase method for P-channel charge trapping memory device Jun 1, 2004 Issued
Array ( [id] => 7054914 [patent_doc_number] => 20050276086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-15 [patent_title] => 'Ternary CAM cell for reduced matchline capacitance' [patent_app_type] => utility [patent_app_number] => 10/856783 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9585 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20050276086.pdf [firstpage_image] =>[orig_patent_app_number] => 10856783 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/856783
Ternary CAM cell for reduced matchline capacitance May 31, 2004 Issued
Array ( [id] => 7342609 [patent_doc_number] => 20040246807 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-09 [patent_title] => 'Multi-port memory device with stacked banks' [patent_app_type] => new [patent_app_number] => 10/858659 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3557 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0246/20040246807.pdf [firstpage_image] =>[orig_patent_app_number] => 10858659 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/858659
Multi-port memory device with stacked banks May 31, 2004 Issued
Array ( [id] => 7115521 [patent_doc_number] => 20050068822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-31 [patent_title] => 'Memory device and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/858498 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6829 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20050068822.pdf [firstpage_image] =>[orig_patent_app_number] => 10858498 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/858498
Memory device and its manufacturing method May 31, 2004 Issued
Array ( [id] => 7220521 [patent_doc_number] => 20050254318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-17 [patent_title] => 'MEMORY DEVICE HAVING DELAY LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 10/857618 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 6500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0254/20050254318.pdf [firstpage_image] =>[orig_patent_app_number] => 10857618 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/857618
Memory device having delay locked loop May 31, 2004 Issued
Array ( [id] => 7024092 [patent_doc_number] => 20050018486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Semiconductor memory device and electric device with the same' [patent_app_type] => utility [patent_app_number] => 10/856986 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5737 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20050018486.pdf [firstpage_image] =>[orig_patent_app_number] => 10856986 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/856986
Semiconductor memory device and electric device with the same May 31, 2004 Issued
Array ( [id] => 7087712 [patent_doc_number] => 20050007824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Novel two-transistor flash cell for large endurance application' [patent_app_type] => utility [patent_app_number] => 10/858020 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9754 [patent_no_of_claims] => 84 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20050007824.pdf [firstpage_image] =>[orig_patent_app_number] => 10858020 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/858020
Two-transistor flash cell for large endurance application May 31, 2004 Issued
Array ( [id] => 498834 [patent_doc_number] => 07212423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-01 [patent_title] => 'Memory agent core clock aligned to lane' [patent_app_type] => utility [patent_app_number] => 10/858850 [patent_app_country] => US [patent_app_date] => 2004-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 34 [patent_no_of_words] => 16404 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/212/07212423.pdf [firstpage_image] =>[orig_patent_app_number] => 10858850 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/858850
Memory agent core clock aligned to lane May 30, 2004 Issued
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