Richard M. Lorence

Array ( [id] => 6982111 [patent_doc_number] => 20050152180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Separate write and read access architecture for a magnetic tunnel junction' [patent_app_type] => utility [patent_app_number] => 10/754880 [patent_app_country] => US [patent_app_date] => 2004-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4368 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20050152180.pdf [firstpage_image] =>[orig_patent_app_number] => 10754880 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6982112 [patent_doc_number] => 20050152181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Tunneling anisotropic magnetoresistive device and method of operation' [patent_app_type] => utility [patent_app_number] => 10/754882 [patent_app_country] => US [patent_app_date] => 2004-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6054 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20050152181.pdf [firstpage_image] =>[orig_patent_app_number] => 10754882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7274305 [patent_doc_number] => 20040233756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'Synchronous semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/750506 [patent_app_country] => US [patent_app_date] => 2003-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3000 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233756.pdf [firstpage_image] =>[orig_patent_app_number] => 10750506 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7225504 [patent_doc_number] => 20040156257 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Refresh control for semiconductor memory device' [patent_app_type] => new [patent_app_number] => 10/747402 [patent_app_country] => US [patent_app_date] => 2003-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9430 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20040156257.pdf [firstpage_image] =>[orig_patent_app_number] => 10747402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7616116 [patent_doc_number] => 06947328 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-09-20 [patent_title] => 'Voltage level shifter' [patent_app_type] => utility [patent_app_number] => 10/747802 [patent_app_country] => US [patent_app_date] => 2003-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2103 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/947/06947328.pdf [firstpage_image] =>[orig_patent_app_number] => 10747802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1019840 [patent_doc_number] => 06891763 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-10 [patent_title] => 'Input buffer with differential amplifier' [patent_app_type] => utility [patent_app_number] => 10/744804 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7386 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891763.pdf [firstpage_image] =>[orig_patent_app_number] => 10744804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7619125 [patent_doc_number] => 06944064 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Memory unit having programmable device ID' [patent_app_type] => utility [patent_app_number] => 10/744504 [patent_app_country] => US [patent_app_date] => 2003-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2014 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944064.pdf [firstpage_image] =>[orig_patent_app_number] => 10744504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 952060 [patent_doc_number] => 06961267 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-11-01 [patent_title] => 'Method and device for programming cells in a memory array in a narrow distribution' [patent_app_type] => utility [patent_app_number] => 10/738301 [patent_app_country] => US [patent_app_date] => 2003-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3738 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/961/06961267.pdf [firstpage_image] =>[orig_patent_app_number] => 10738301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7293541 [patent_doc_number] => 20040213073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-28 [patent_title] => 'Data input unit of synchronous semiconductor memory device, and data input method using the same' [patent_app_type] => new [patent_app_number] => 10/734804 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2766 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20040213073.pdf [firstpage_image] =>[orig_patent_app_number] => 10734804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7172579 [patent_doc_number] => 20050122822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Random access memory with optional inaccessible memory cells' [patent_app_type] => utility [patent_app_number] => 10/727406 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5334 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122822.pdf [firstpage_image] =>[orig_patent_app_number] => 10727406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1054769 [patent_doc_number] => 06859406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-22 [patent_title] => 'Dynamic RAM semiconductor memory and method for operating the memory' [patent_app_type] => utility [patent_app_number] => 10/724906 [patent_app_country] => US [patent_app_date] => 2003-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2762 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/859/06859406.pdf [firstpage_image] =>[orig_patent_app_number] => 10724906 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6937701 [patent_doc_number] => 20050111262 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'NON-VOLATILE MEMORY AND METHOD OF OPERATION' [patent_app_type] => utility [patent_app_number] => 10/707108 [patent_app_country] => US [patent_app_date] => 2003-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3765 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20050111262.pdf [firstpage_image] =>[orig_patent_app_number] => 10707108 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7302441 [patent_doc_number] => 20040114418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Ferroelectric memory and method of reading data in the same' [patent_app_type] => new [patent_app_number] => 10/716705 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7450 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0114/20040114418.pdf [firstpage_image] =>[orig_patent_app_number] => 10716705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7225424 [patent_doc_number] => 20040156242 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-12 [patent_title] => 'Nonvolatile memory' [patent_app_type] => new [patent_app_number] => 10/716504 [patent_app_country] => US [patent_app_date] => 2003-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5368 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20040156242.pdf [firstpage_image] =>[orig_patent_app_number] => 10716504 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7284653 [patent_doc_number] => 20040145947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Circuit for programming a non-volatile memory device with adaptive program load control' [patent_app_type] => new [patent_app_number] => 10/706306 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6743 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0145/20040145947.pdf [firstpage_image] =>[orig_patent_app_number] => 10706306 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7376557 [patent_doc_number] => 20040080976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Non-volatile semiconductor memory' [patent_app_type] => new [patent_app_number] => 10/703503 [patent_app_country] => US [patent_app_date] => 2003-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11784 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20040080976.pdf [firstpage_image] =>[orig_patent_app_number] => 10703503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7306349 [patent_doc_number] => 20040141377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Nonvolatile semiconductor memory device and data program method thereof' [patent_app_type] => new [patent_app_number] => 10/700508 [patent_app_country] => US [patent_app_date] => 2003-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8250 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0141/20040141377.pdf [firstpage_image] =>[orig_patent_app_number] => 10700508 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7459160 [patent_doc_number] => 20040094778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Semiconductor device and semiconductor memory device provided with internal current setting adjustment circuit' [patent_app_type] => new [patent_app_number] => 10/694780 [patent_app_country] => US [patent_app_date] => 2003-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 31243 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20040094778.pdf [firstpage_image] =>[orig_patent_app_number] => 10694780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1036141 [patent_doc_number] => 06876587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/694402 [patent_app_country] => US [patent_app_date] => 2003-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5254 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/876/06876587.pdf [firstpage_image] =>[orig_patent_app_number] => 10694402 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 994858 [patent_doc_number] => 06917560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Reduction of capacitive effects in a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/691707 [patent_app_country] => US [patent_app_date] => 2003-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 24 [patent_no_of_words] => 10809 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/917/06917560.pdf [firstpage_image] =>[orig_patent_app_number] => 10691707 [rel_patent_id] =>[rel_patent_doc_number] =>)